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revision date: mar. 17 , 2004 16 h8s/2172 group hardware manual renesas 16-bit single-chip microcomputer h8s family/h8s/2100 series h8s/2170 HD64F2170 rev.2.00 rej09b0149-0200z
rev. 2.00, 03/04, page ii of xxxii
rev. 2.00, 03/04, page iii of xxxii 1. these materials are intended as a reference to assist our customers in the selection of the renesas technology corp. product best suited to the customer's application; they do not convey any license under any intellectual property rights, or any other rights, belonging to renesas technology corp. or a third party. 2. renesas technology corp. assumes no responsibility for any damage, or infringement of any third- party's rights, originating in the use of any product data, diagrams, charts, programs, algorithms, or circuit application examples contained in these materials. 3. all information contained in these materials, including product data, diagrams, charts, programs and algorithms represents information on products at the time of publication of these materials, and are subject to change by renesas technology corp. without notice due to product improvements or other reasons. it is therefore recommended that customers contact renesas technology corp. or an authorized renesas technology corp. product distributor for the latest product information before purchasing a product listed herein. the information described here may contain technical inaccuracies or typographical errors. renesas technology corp. assumes no responsibility for any damage, liability, or other loss rising from these inaccuracies or errors. please also pay attention to information published by renesas technology corp. by various means, including the renesas technology corp. semiconductor home page (http://www.renesas.com). 4. when using any or all of the information contained in these materials, including product data, diagrams, charts, programs, and algorithms, please be sure to evaluate all information as a total system before making a final decision on the applicability of the information and products. renesas technology corp. assumes no responsibility for any damage, liability or other loss resulting from the information contained herein. 5. renesas technology corp. semiconductors are not designed or manufactured for use in a device or system that is used under circumstances in which human life is potentially at stake. please contact renesas technology corp. or an authorized renesas technology corp. product distributor when considering the use of a product contained herein for any specific purposes, such as apparatus or systems for transportation, vehicular, medical, aerospace, nuclear, or undersea repeater use. 6. the prior written approval of renesas technology corp. is necessary to reprint or reproduce in whole or in part these materials. 7. if these products or technologies are subject to the japanese export control restrictions, they must be exported under a license from the japanese government and cannot be imported into a country other than the approved destination. any diversion or reexport contrary to the export control laws and regulations of japan and/or the country of destination is prohibited. 8. please contact renesas technology corp. for further details on these materials or the products contained therein. 1. renesas technology corp. puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. trouble with semiconductors may lead to personal injury, fire or property damage. remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of nonflammable material or (iii) prevention against any malfunction or mishap. keep safety first in your circuit designs! notes regarding these materials
rev. 2.00, 03/04, page iv of xxxii general precautions on handling of product 1. treatment of nc pins note: do not connect anything to the nc pins. the nc (not connected) pins are either not connected to any of the internal circuitry or are used as test pins or to reduce noise. if something is connected to the nc pins, the operation of the lsi is not guaranteed. 2. treatment of unused input pins note: fix all unused input pins to high or low level. generally, the input pins of cmos products are high-impedance input pins. if unused pins are in their open states, intermediate levels are induced by noise in the vicinity, a pass- through current flows internally, and a malfunction may occur. 3. processing before initialization note: when power is first supplied, the product's state is undefined. the states of internal circuits are undefined until full power is supplied throughout the chip and a low level is input on the reset pi n. during the period where the states are undefined, the register settings and the output state of each pin are also undefined. design your system so that it does not malfunction because of processing while it is in this undefined state. for those products which have a reset function, reset the lsi immediately after the power supply has been turned on. 4. prohibition of access to undefined or reserved addresses note: access to undefined or reserved addresses is prohibited. the undefined or reserved addresses may be used to expand functions, or test registers may have been be allocated to these addresse s. do not access these registers; the system's operation is not guaranteed if they are accessed.
rev. 2.00, 03/04, page v of xxxii configuration of this manual this manual comprises the following items: 1. general precautions on handling of product 2. configuration of this manual 3. preface 4. contents 5. overview 6. description of functional modules ? cpu and system-control modules ? on-chip peripheral modules the configuration of the functional description of each module differs according to the module. however, the generic style includes the following items: i) feature ii) input/output pin iii) register description iv) operation v) usage note when designing an application system that includes this lsi, take notes into account. each section includes notes in relation to the descriptions given, and usage notes are given, as required, as the final part of each section. 7. list of registers 8. electrical characteristics 9. appendix 10. main revisions and additions in this edition (only for revised versions) the list of revisions is a summary of points that have been revised or added to earlier versions. this does not include all of the revised contents . for details, see the actual locations in this manual. 11. index
rev. 2.00, 03/04, page vi of xxxii preface this lsi is a microcomputer (mcu) made up of the h8s/2000 cpu employing renesas technolgy's original architecture as its core, and the peripheral functions required to configure a system. the h8s/2000 cpu has an internal 32-bit configuration, sixteen 16-bit general registers, and a simple and optimized instruction set for high-speed operation. the h8s/2000 cpu can handle a 16-mbyte linear address space. this lsi is equipped with rom and ram memory , direct memory access co ntroller (dmac) bus master, an 8-bit timer (tmr), a watchdog timer (w dt), a universal serial bus 2 (usb2), a serial communication interface for boot mode (sci), and i/o ports as on-chip peripheral modules required for system configuration. a flash memory (f-ztat tm *) version is available for this lsi's rom. the f-ztat version provides flexibility as it can be reprogrammed in no time to cope with all situations from the early stages of mass production to full-scale mass production. this is particularly applicable to application devices with specifications that will most probably change. this manual describes this lsi's hardware. note: * f-ztat tm is a trademark of renesas technolgy. corp. target users: this manual was written for users who will be using this lsi in the design of application systems. target users are expected to understand the fundamentals of electrical circuits, logical ci rcuits, and microcomputers. objective: this manual was written to explain the hardware functions and electrical characteristics of this ls i to the target users. refer to the h8s/2600 series, h8s/2000 series programming manual for a detailed description of the instruction set. notes on reading this manual: ? in order to understand the overall functions of the chip read the manual according to the contents. this manual can be roughly categorized into parts on the cpu, system control functions, peripher al functions, and elect rical characteristics. ? in order to understand the details of the cpu's functions read the h8s/2600 series, h8s/ 2000 series programming manual. ? in order to understand the details of a register when its name is known read the index that is the final part of the manual to find the page number of the entry on the register. the addresses, bits, and initial values of the registers are summarized in section 17, list of registers.
rev. 2.00, 03/04, page vii of xxxii examples: register name: the following notatio n is used for cases when the same or a similar function, e.g. dmac or serial communication interface, is implemented on more than one channel: xxx_n (xxx is the register name and n is the channel number) bit order: the msb is on the left and the lsb is on the right. number notation: binary is b?xxxx, hexadecimal is h?xxxx. signal notation: an overbar is added to a low-active signal: xxxx related manuals: the latest versions of all related manuals are available from our web site. please ensure you have the latest versions of all documents you require. (http://www.renesas.com/eng/) h8s/2170 f-ztat tm manuals: document title document no. h8s/2172 series h8s/2170 f-ztat tm hardware manual this manual h8s/2600 series, h8s/2000 series programming manual ade-602-083 user's manuals for development tools: document title document no. h8s, h8/300 series c/c++ compiler, assembler, optimizing linkage editor user's manual ade-702-247 h8s, h8/300 series simulator/debugger user's manual ade-702-282 h8s, h8/300 series high-performance embedded workshop, high-performance debugging interface tutorial ade-702-231 high-performance embedded workshop user's manual ade-702-201
rev. 2.00, 03/04, page viii of xxxii
rev. 2.00, 03/04, page ix of xxxii contents section 1 overview............................................................................................1 1.1 features....................................................................................................................... ...... 1 1.2 internal bloc k diagram..................................................................................................... 2 1.3 pin descri ption................................................................................................................ .. 3 1.3.1 pin arrangement .................................................................................................. 3 1.3.2 pin arrangements in each mode ......................................................................... 4 1.3.3 pin functions ....................................................................................................... 8 section 2 cpu....................................................................................................13 2.1 features....................................................................................................................... ...... 13 2.1.1 differences between h8s/2600 cpu and h8s/2000 cpu .................................. 14 2.1.2 differences from h8/300 cpu ............................................................................ 15 2.1.3 differences from h8/300h cpu.......................................................................... 15 2.2 cpu operating modes...................................................................................................... 16 2.2.1 normal mode....................................................................................................... 16 2.2.2 advanced mode................................................................................................... 18 2.3 address space.................................................................................................................. .20 2.4 register conf iguratio n...................................................................................................... 21 2.4.1 general registers................................................................................................. 22 2.4.2 program counter (pc) ......................................................................................... 23 2.4.3 extended control re gister (exr) ....................................................................... 23 2.4.4 condition-code re gister (ccr).......................................................................... 24 2.4.5 initial register values.......................................................................................... 25 2.5 data formats................................................................................................................... .. 26 2.5.1 general register data formats ............................................................................ 26 2.5.2 memory data formats ......................................................................................... 28 2.6 instruction set ................................................................................................................ ... 29 2.6.1 table of instructions cl assified by function ....................................................... 30 2.6.2 basic instructio n formats .................................................................................... 39 2.7 addressing modes and effec tive address ca lculation..................................................... 40 2.7.1 register direct # rn ............................................................................................ 41 2.7.2 register indirect # @ern .................................................................................... 41 2.7.3 register indirect with displacement # @(d:16, ern) or @(d:32, ern).............. 41 2.7.4 register indirect with post -increment or pre-decrement # @ern+ or @-ern ........................................................................................... 41 2.7.5 absolute address # @aa:8, @aa:16, @aa: 24, or @aa:32.................................... 41 2.7.6 immediate # #xx:8, #xx:16, or #xx:32................................................................. 42 2.7.7 program-counter relative # @(d:8, pc) or @(d:16, pc).................................... 42 2.7.8 memory indirect # @@aa:8 ................................................................................ 42
rev. 2.00, 03/04, page x of xxxii 2.7.9 effective address calculation ............................................................................. 44 2.8 processing states.............................................................................................................. .46 2.9 usage note..................................................................................................................... ... 47 2.9.1 note on bit manipula tion instructions ................................................................ 47 section 3 mcu operating modes ..................................................................... 49 3.1 operating mode selection ................................................................................................ 49 3.2 register desc riptions........................................................................................................ 50 3.2.1 mode control regi ster (mdcr) ......................................................................... 50 3.2.2 system control re gister (s yscr)...................................................................... 51 3.3 operating modes............................................................................................................... 5 2 3.3.1 mode 2................................................................................................................. 52 3.3.2 pin functions ....................................................................................................... 52 3.4 address map .................................................................................................................... .53 section 4 exception handling ........................................................................... 55 4.1 exception handling t ypes and priority............................................................................ 55 4.2 exception sources and ex ception vector table ............................................................... 56 4.3 reset .......................................................................................................................... ....... 57 4.3.1 reset exceptio n handling ................................................................................... 57 4.3.2 interrupts after reset............................................................................................ 58 4.3.3 on-chip peripheral modules af ter reset is cancelled ........................................ 58 4.4 interrupt exception handling ........................................................................................... 59 4.5 trap instruction ex ception ha ndling................................................................................ 59 4.6 stack status after ex ception ha ndling.............................................................................. 60 4.7 usage note..................................................................................................................... ... 60 section 5 interrupt controller............................................................................ 63 5.1 features....................................................................................................................... ...... 63 5.2 input/output pins.............................................................................................................. 64 5.3 register desc riptions........................................................................................................ 64 5.3.1 interrupt control registers a to c (icra to icrc) ........................................... 64 5.3.2 address break control register (a brkcr) ...................................................... 65 5.3.3 break address registers a to c (pbara to pbarc) ....................................... 66 5.3.4 irq sense control register s h, l (iscrh, iscrl) .......................................... 67 5.3.5 irq enable register (ier) .................................................................................. 68 5.3.6 irq status regi ster (isr).................................................................................... 68 5.4 interrupt sources.............................................................................................................. .69 5.4.1 external interrupts ............................................................................................... 69 5.4.2 internal interrupts ................................................................................................ 70 5.5 interrupt exception hand ling vector table...................................................................... 70 5.6 interrupt control modes an d interrupt operation ............................................................. 72 5.6.1 interrupt control mode 0..................................................................................... 74
rev. 2.00, 03/04, page xi of xxxii 5.6.2 interrupt control mode 1 ..................................................................................... 76 5.6.3 interrupt exception handling sequence .............................................................. 78 5.6.4 interrupt respon se times .................................................................................... 80 5.7 usage notes .................................................................................................................... .. 81 5.7.1 conflict between interrupt ge neration and disabling ......................................... 81 5.7.2 instructions that di sable interrupts ...................................................................... 82 5.7.3 interrupts during execution of eepmov in struction.......................................... 82 section 6 bus controller (bsc).........................................................................83 6.1 features....................................................................................................................... ...... 83 6.2 input/output pins .............................................................................................................. 85 6.3 register desc riptions ........................................................................................................ 86 6.3.1 access control regi ster (acscr) ...................................................................... 87 6.3.2 cs assertion period cont rol register (csacr)................................................. 88 6.3.3 wait control regi ster (wtcr) ........................................................................... 90 6.3.4 bus control regi ster ( bcr) ................................................................................ 92 6.3.5 read strobe timing cont rol register (rdncr) ................................................ 93 6.3.6 dram control regi ster (dramcr) ................................................................. 94 6.3.7 dram access control register (draccr)...................................................... 97 6.3.8 refresh control re gister (r efcr) ..................................................................... 98 6.3.9 refresh timer coun ter (rtcnt)........................................................................ 101 6.3.10 refresh time constant register (rtcor) ......................................................... 101 6.4 bus control .................................................................................................................... ... 102 6.4.1 area division....................................................................................................... 102 6.4.2 address ma p ........................................................................................................ 103 6.4.3 bus specifica tions................................................................................................ 105 6.4.4 memory inte rfaces............................................................................................... 107 6.4.5 chip select signals .............................................................................................. 108 6.5 basic bus in terface ........................................................................................................... 1 09 6.5.1 data size and data alignment............................................................................. 109 6.5.2 valid strobes ....................................................................................................... 110 6.5.3 basic timi ng........................................................................................................ 110 6.5.4 wait cont rol ........................................................................................................ 119 6.5.5 read strobe ( rd ) timing.................................................................................... 120 6.5.6 extension of chip select ( cs ) assertion period.................................................. 121 6.6 dram interface ............................................................................................................... 12 2 6.6.1 setting dram space........................................................................................... 122 6.6.2 address multip lexing .......................................................................................... 122 6.6.3 data bus............................................................................................................... 123 6.6.4 pins used for dr am interface............................................................................ 123 6.6.5 basic timi ng........................................................................................................ 124 6.6.6 column address output cycle control ............................................................... 125 6.6.7 row address output state control...................................................................... 126
rev. 2.00, 03/04, page xii of xxxii 6.6.8 precharge state control ....................................................................................... 128 6.6.9 wait contro l ........................................................................................................ 129 6.6.10 byte access control ............................................................................................ 131 6.6.11 burst opera tion.................................................................................................... 132 6.6.12 refresh control.................................................................................................... 137 6.6.13 dmac single address transfer mode and dram interface............................. 140 6.7 idle cycle..................................................................................................................... ..... 142 6.7.1 operation ............................................................................................................. 142 6.7.2 pin states in id le cycle........................................................................................ 149 6.8 write data buffe r function .............................................................................................. 150 6.9 bus arbitr ation ................................................................................................................ .151 6.9.1 operation ............................................................................................................. 151 6.9.2 bus transfer timing............................................................................................ 151 6.10 bus controller operat ion in reset .................................................................................... 152 section 7 dma controller (dmac)................................................................. 153 7.1 features....................................................................................................................... ...... 153 7.2 input/output pins.............................................................................................................. 155 7.3 register desc riptions........................................................................................................ 15 7 7.3.1 dma source address regi ster (dmsar).......................................................... 158 7.3.2 dma destination address register (dmdar) .................................................. 158 7.3.3 dma transfer count re gister (d mtcr)........................................................... 158 7.3.4 dma mode control re gister (d mmdr) ........................................................... 160 7.3.5 dma address control re gister (d macr) ........................................................ 165 7.3.6 usb transfer control register (u stcr) ........................................................... 169 7.4 operation ...................................................................................................................... .... 171 7.4.1 transfer modes.................................................................................................... 171 7.4.2 address modes (dual address mo de/single address mode) ............................. 172 7.4.3 dma transfer requests (auto request mode/external request mode/usb transfer request) ............... 176 7.4.4 bus modes (cycle steal mode/burst mode) ....................................................... 177 7.4.5 transfer modes (normal transfer mode/block transfer mode) ........................ 178 7.4.6 repeat area f unction .......................................................................................... 179 7.4.7 registers during dma tr ansfer operation ......................................................... 182 7.4.8 channel prio rity................................................................................................... 186 7.4.9 dmac bus cycles (dua l address mo de)........................................................... 189 7.4.10 dmac bus cycles (singl e address mode) ........................................................ 196 7.4.11 examples of operation ti ming in each mode .................................................... 201 7.4.12 ending dma tr ansfer ......................................................................................... 212 7.4.13 relationship between dmac an d other bus masters ........................................ 213 7.5 interrupt sources.............................................................................................................. .213 7.6 usage notes .................................................................................................................... .. 216
rev. 2.00, 03/04, page xiii of xxxii section 8 i/o ports .............................................................................................219 8.1 port 1......................................................................................................................... ........ 222 8.1.1 port 1 data direction register (p1ddr)............................................................. 222 8.1.2 port 1 data regi ster (p1dr)................................................................................ 223 8.1.3 port 1 register (port1)...................................................................................... 223 8.1.4 pin functions ....................................................................................................... 224 8.2 port 2......................................................................................................................... ........ 226 8.2.1 port 2 data direction register (p2ddr)............................................................. 226 8.2.2 port 2 data regi ster (p2dr)................................................................................ 226 8.2.3 port 2 register (port2)...................................................................................... 227 8.2.4 pin functions ....................................................................................................... 227 8.3 port 3......................................................................................................................... ........ 230 8.3.1 port 3 data direction register (p3ddr)............................................................. 230 8.3.2 port 3 data regi ster (p3dr)................................................................................ 230 8.3.3 port 3 register (port3)...................................................................................... 231 8.3.4 pin functions ....................................................................................................... 231 8.4 port 4......................................................................................................................... ........ 233 8.4.1 port 4 data direction register (p4ddr)............................................................. 233 8.4.2 port 4 data regi ster (p4dr)................................................................................ 234 8.4.3 port 4 register (port4)...................................................................................... 234 8.4.4 pin functions ....................................................................................................... 235 8.5 port 5......................................................................................................................... ........ 237 8.5.1 port 5 data direction register (p5ddr)............................................................. 237 8.5.2 port 5 data regi ster (p5dr)................................................................................ 237 8.5.3 port 5 register (port5)...................................................................................... 238 8.5.4 pin functions ....................................................................................................... 238 8.6 port 6......................................................................................................................... ........ 242 8.6.1 port 6 data direction register (p6ddr)............................................................. 242 8.6.2 port 6 data regi ster (p6dr)................................................................................ 242 8.6.3 port 6 register (port6)...................................................................................... 243 8.6.4 pin functions ....................................................................................................... 243 8.7 port 7......................................................................................................................... ........ 246 8.7.1 port 7 data direction register (p7ddr)............................................................. 246 8.7.2 port 7 data regi ster (p7dr)................................................................................ 247 8.7.3 port 7 register (port7)...................................................................................... 247 8.7.4 pin functions ....................................................................................................... 248 8.8 port 8......................................................................................................................... ........ 251 8.8.1 port 8 data direction register (p8ddr)............................................................. 251 8.8.2 port 8 data regi ster (p8dr)................................................................................ 251 8.8.3 port 8 register (port8)...................................................................................... 252 8.8.4 pin functions ....................................................................................................... 252 8.9 port 9......................................................................................................................... ........ 254 8.9.1 port 9 data direction register (p9ddr)............................................................. 254
rev. 2.00, 03/04, page xiv of xxxii 8.9.2 port 9 data regi ster (p9dr) ............................................................................... 255 8.9.3 port 9 register (port9)...................................................................................... 255 8.9.4 pin functio ns ....................................................................................................... 256 8.10 port a......................................................................................................................... ....... 258 8.10.1 port a data direction register (p addr)........................................................... 258 8.10.2 port a data regi ster (padr).............................................................................. 258 8.10.3 port a register (porta).................................................................................... 259 8.10.4 pin functio ns ....................................................................................................... 259 8.11 pin sel ection .................................................................................................................. ... 261 8.11.1 port function control re gister 1 (pfcr1).......................................................... 261 8.11.2 irq sense port select register (issr) ............................................................... 262 section 9 8-bit timer (tmr)............................................................................ 263 9.1 features....................................................................................................................... ...... 263 9.2 input/output pins.............................................................................................................. 265 9.3 register desc riptions........................................................................................................ 26 5 9.3.1 timer counter (tcnt)........................................................................................ 265 9.3.2 time constant regist er a (tcora) .................................................................. 266 9.3.3 time constant regi ster b (t corb)................................................................... 266 9.3.4 timer control regi ster (tcr)............................................................................. 266 9.3.5 timer control/status re gister (tcsr)................................................................ 268 9.4 operation ...................................................................................................................... .... 270 9.4.1 pulse outp ut ........................................................................................................ 270 9.5 operation timing.............................................................................................................. 2 71 9.5.1 tcnt incrementa tion timi ng ............................................................................. 271 9.5.2 timing of cmfa and cmfb setting when compare-match occurs ................. 272 9.5.3 timing of timer output when compare-match occurs...................................... 272 9.5.4 timing of compar e match cl ear......................................................................... 273 9.5.5 timing of tcnt ex ternal reset.......................................................................... 273 9.5.6 timing of overflow fl ag (ovf) se tting ............................................................. 273 9.6 operation with cascad ed connection............................................................................... 274 9.6.1 16-bit counter mode........................................................................................... 274 9.6.2 compare match co unt mode .............................................................................. 275 9.7 interrupt sources.............................................................................................................. .275 9.7.1 interrupt sources.................................................................................................. 275 9.8 usage notes .................................................................................................................... .. 276 9.8.1 contention between tcnt write and clear........................................................ 276 9.8.2 contention between tcnt wr ite and incr ement ................................................ 277 9.8.3 contention between tcor write and compare match ...................................... 278 9.8.4 contention between compar e matches a and b ................................................. 279 9.8.5 switching of internal clocks and tcnt op eration ............................................ 279 9.8.6 mode setting with casc aded connec tion ............................................................ 281 9.8.7 interrupts in module stop mode.......................................................................... 281
rev. 2.00, 03/04, page xv of xxxii section 10 watchdog timer (wdt)..................................................................283 10.1 features....................................................................................................................... ...... 283 10.2 register desc riptions ........................................................................................................ 28 4 10.2.1 timer counter (tcnt)........................................................................................ 284 10.2.2 timer control/status re gister (tcsr)................................................................ 284 10.3 operation ...................................................................................................................... .... 286 10.3.1 watchdog time r mode ........................................................................................ 286 10.3.2 interval timer mode............................................................................................ 287 10.3.3 watchdog timer overflow flag (ovf) timing.................................................. 288 10.4 interrupt sources.............................................................................................................. .288 10.5 usage notes .................................................................................................................... .. 289 10.5.1 notes on regist er access..................................................................................... 289 10.5.2 conflict between timer counter (t cnt) write and increment.......................... 290 10.5.3 changing values of ck s2 to cks0 bits............................................................. 290 10.5.4 switching between watchdog timer m ode and interval timer mode................ 290 section 11 serial communication in terface for boot mode (sci) ...................291 11.1 features....................................................................................................................... ...... 291 11.2 input/output pins .............................................................................................................. 292 11.3 register desc riptions ........................................................................................................ 29 3 11.3.1 receive shift regi ster (rsr) .............................................................................. 293 11.3.2 receive data regi ster (rdr) .............................................................................. 293 11.3.3 transmit data regi ster (tdr)............................................................................. 293 11.3.4 transmit shift regi ster (tsr) ............................................................................. 294 11.3.5 serial mode regi ster (smr) ............................................................................... 294 11.3.6 serial control re gister (s cr) ............................................................................. 295 11.3.7 serial status regi ster (ssr) ................................................................................ 297 11.3.8 bit rate regist er (brr) ...................................................................................... 300 11.4 operation in asynch ronous mode .................................................................................... 304 11.4.1 data transfer format........................................................................................... 305 11.4.2 receive data sampling timing and reception margin in asynchronous mode ............................................................................................ 306 11.4.3 clock.................................................................................................................... 307 11.4.4 sci initialization (async hronous mode) ............................................................. 307 11.4.5 data transmission (as ynchronous mode)........................................................... 308 11.4.6 serial data reception (a synchronous mode)...................................................... 310 11.5 interrupt sources.............................................................................................................. .314 11.5.1 interrupts in normal serial co mmunication interface mode .............................. 314 11.6 usage notes .................................................................................................................... .. 315 11.6.1 module stop mode setting .................................................................................. 315 11.6.2 relation between writes to td r and the tdre flag ......................................... 315 11.6.3 operation in case of mode transition................................................................. 315
rev. 2.00, 03/04, page xvi of xxxii section 12 universal serial bus 2 (usb2)........................................................ 319 12.1 features....................................................................................................................... ...... 319 12.2 input/output signals ......................................................................................................... 32 1 12.3 register desc riptions........................................................................................................ 32 2 12.3.1 interrupt flag regi ster 0 (ifr0) .......................................................................... 323 12.3.2 interrupt select regi ster 0 (isr0)........................................................................ 328 12.3.3 interrupt enable regi ster 0 (ier0) ...................................................................... 329 12.3.4 ep0o receive data size register (epsz0o) ....................................................... 329 12.3.5 ep1 receive data size register (e psz1) ........................................................... 330 12.3.6 ep0i data regist er (epdr0i).............................................................................. 330 12.3.7 ep0o data regist er (epdr0o) ............................................................................ 330 12.3.8 ep0s data regist er (epdr0s) ............................................................................. 331 12.3.9 ep1 data register (epdr1) ................................................................................ 331 12.3.10 ep2 data register (epdr2) ................................................................................ 331 12.3.11 ep3 data register (epdr3) ................................................................................ 332 12.3.12 data status regist er 0 (dasts0)........................................................................ 332 12.3.13 packet enable regist er 0i (pkte0i).................................................................... 333 12.3.14 packet enable regist er 2 (pkte2)...................................................................... 333 12.3.15 packet enable regist er 3 (pkte3)...................................................................... 333 12.3.16 fifo clear register 0 (fclr0) .......................................................................... 334 12.3.17 endpoint stall regist er 0 (epstl0).................................................................... 336 12.3.18 dma set register 0 (dma 0).............................................................................. 336 12.3.19 control register (ctrl) ..................................................................................... 337 12.3.20 port function control re gister 3 (pfcr3).......................................................... 338 12.3.21 usb suspend status regi ster (usbsusp) ......................................................... 338 12.4 interrupt pins ................................................................................................................. ... 340 12.4.1 usbi0 interrupt ................................................................................................... 340 12.4.2 usbi1 interrupt ................................................................................................... 340 12.5 communication op eration................................................................................................ 341 12.5.1 usb cable conn ection........................................................................................ 341 12.5.2 usb cable disco nnection ................................................................................... 342 12.5.3 control tran sfer................................................................................................... 343 12.5.4 ep1 bulk-out transfer (dual fifo) ................................................................... 349 12.5.5 ep2 bulk-in transfer (dual fifo)...................................................................... 351 12.5.6 ep3 interrupt-in transfer..................................................................................... 353 12.5.7 processing of usb standard request s and class/vendor requests.................... 354 12.5.8 stall opera tions ................................................................................................... 355 12.5.9 tree configur ation............................................................................................... 358 12.5.10 power supply sp ecificatio n................................................................................. 358 12.6 notes on usin g dma ....................................................................................................... 358 12.7 transition to usb suspend mode .................................................................................... 359 12.7.1 suspend signal output......................................................................................... 359 12.7.2 software standby in suspend mode .................................................................... 361
rev. 2.00, 03/04, page xvii of xxxii 12.8 usage notes .................................................................................................................... .. 364 12.8.1 setup data re ception........................................................................................... 364 12.8.2 fifo cl ear ........................................................................................................... 364 12.8.3 operating frequency............................................................................................ 364 12.8.4 interrupts.............................................................................................................. 364 12.8.5 register acces s size ............................................................................................ 364 12.8.6 data register overre ad or overwrite .................................................................. 365 12.8.7 ep0 interrupt sources assignment ...................................................................... 365 12.8.8 fifo size at full speed mode............................................................................. 365 12.8.9 level shifter for vbus pin................................................................................. 366 12.8.10 usb 2.0 transceiver (p hysical la yer) ................................................................ 366 12.8.11 epdr0s read ...................................................................................................... 366 12.8.12 usb bus idle in hi gh-speed mode..................................................................... 366 12.8.13 note on usb bus disconnecti on......................................................................... 367 12.8.14 example of extern al circuit ................................................................................ 367 12.8.15 external physical layer lsi ................................................................................ 368 12.8.16 operation at the bus reset recep tion.................................................................. 368 12.8.17 usage notes in contro l in transfer .................................................................... 369 12.8.18 usb interrupt during software st andby ............................................................. 369 section 13 ram ................................................................................................371 section 14 flash memory (0.18- $ m f-ztat version) ....................................373 14.1 features....................................................................................................................... ...... 373 14.1.1 operating mode ................................................................................................... 375 14.1.2 mode comparison................................................................................................ 376 14.1.3 flash mat configuration.................................................................................... 377 14.1.4 block divi sion ..................................................................................................... 378 14.1.5 programming/erasing interface ........................................................................... 379 14.2 input/output pins .............................................................................................................. 381 14.3 register desc riptions ........................................................................................................ 38 1 14.3.1 programming/erasing in terface regi ster............................................................. 382 14.3.2 programming/erasing inte rface parameter .......................................................... 391 14.4 on-board progra mming m ode ......................................................................................... 401 14.4.1 boot mode ........................................................................................................... 401 14.4.2 user program mode............................................................................................. 405 14.4.3 user boot mode................................................................................................... 415 14.4.4 procedure program and storable area for programming data ............................ 418 14.5 protection ..................................................................................................................... ..... 428 14.5.1 hardware protection ............................................................................................ 428 14.5.2 software prot ection.............................................................................................. 429 14.5.3 error protection.................................................................................................... 429 14.6 switching between user mat and user boot mat ........................................................ 431
rev. 2.00, 03/04, page xviii of xxxii 14.7 flash memory emula tion in ra m ................................................................................... 432 14.7.1 emulation in ram .............................................................................................. 432 14.7.2 ram overla p ...................................................................................................... 433 14.8 programmer mode ............................................................................................................ 434 14.9 serial communication interface sp ecification for b oot mode......................................... 435 14.10 usage notes .................................................................................................................... .. 461 section 15 clock pulse generator..................................................................... 463 15.1 oscilla tor..................................................................................................................... ...... 463 15.1.1 connecting crystal resonato r ............................................................................. 463 15.1.2 external cloc k input............................................................................................ 464 15.2 pll circuit .................................................................................................................... ... 466 15.3 usage notes .................................................................................................................... .. 467 15.3.1 notes on resonator.............................................................................................. 467 15.3.2 notes on boar d design ........................................................................................ 467 15.3.3 note on confirming the operation ........................................................................ 467 section 16 power-down modes........................................................................ 469 16.1 register desc riptions........................................................................................................ 47 2 16.1.1 standby control regi ster (sby cr) .................................................................... 472 16.1.2 module stop control registers h and l (mstpcrh , mstpcrl) ................... 473 16.2 operation ...................................................................................................................... .... 474 16.2.1 sleep mode .......................................................................................................... 474 16.2.2 software sta ndby mode ....................................................................................... 474 16.2.3 hardware stan dby mode ..................................................................................... 476 16.2.4 module stop mode .............................................................................................. 477 16.3 usage notes .................................................................................................................... .. 478 16.3.1 i/o port st atus...................................................................................................... 478 16.3.2 current consumption duri ng oscillation stabiliza tion standby period .............. 478 16.3.3 on-chip peripheral mo dule interr upts ................................................................ 478 16.3.4 writing to ms tpcr ............................................................................................ 478 section 17 list of registers............................................................................... 479 17.1 register addresses (a ddress order)................................................................................. 480 17.2 register bits.................................................................................................................. .... 485 17.3 register states in ea ch operating mode .......................................................................... 493 section 18 electrical characteristics ................................................................. 497 18.1 absolute maximum ratings ............................................................................................. 497 18.2 dc character istics ............................................................................................................ 4 98 18.3 ac character istics ............................................................................................................ 5 01 18.3.1 clock timing ....................................................................................................... 501 18.3.2 control signal timing ......................................................................................... 503
rev. 2.00, 03/04, page xix of xxxii 18.3.3 bus timing .......................................................................................................... 504 18.3.4 dmac timi ng..................................................................................................... 515 18.3.5 timing of on-chip peri pheral modules .............................................................. 518 18.4 flash memory char acteristic s .......................................................................................... 521 18.4.1 flash memory char acteristi cs ............................................................................. 521 18.5 use note (internal volta ge step down) ........................................................................... 522 appendix .........................................................................................................523 a. port states in each processing state ................................................................................. 523 b. product lineup................................................................................................................. .525 c. package dime nsions ......................................................................................................... 526 main revisions and additions in this edition .....................................................527 index .........................................................................................................531
rev. 2.00, 03/04, page xx of xxxii
rev. 2.00, 03/04, page xxi of xxxii figures section 1 overview figure 1.1 internal block diagram ............................................................................................ ..... 2 figure 1.2 pin arrangement (tfp-100b) ....................................................................................... 3 section 2 cpu figure 2.1 exception vect or table (normal mode)..................................................................... 17 figure 2.2 stack stru cture in normal mode................................................................................. 17 figure 2.3 exception vector table (advanced mode)................................................................. 18 figure 2.4 stack struct ure in advanced mode ............................................................................. 19 figure 2.5 memory map........................................................................................................ ....... 20 figure 2.6 cpu in ternal re gisters ............................................................................................ .... 21 figure 2.7 usage of general registers ........................................................................................ .22 figure 2.8 stack............................................................................................................. ............... 23 figure 2.9 general regi ster data formats (1).............................................................................. 26 figure 2.9 general regi ster data formats (2).............................................................................. 27 figure 2.10 memo ry data formats.............................................................................................. .28 figure 2.11 instruc tion formats (e xamples) ................................................................................ 40 figure 2.12 branch address specificatio n in memory indirect addressing mode ...................... 43 figure 2.13 state tran siti ons ................................................................................................ ........ 47 section 3 mcu operating modes figure 3.1 address map ....................................................................................................... ........ 53 section 4 exception handling figure 4.1 reset se quence.................................................................................................... ........ 58 figure 4.2 stack status after exceptio n handling ........................................................................ 60 figure 4.3 operation wh en sp value is odd................................................................................ 61 section 5 interrupt controller figure 5.1 block diagram of interrupt controller........................................................................ 63 figure 5.2 block diagram of interrupts irq7 to irq0 ................................................................ 69 figure 5.3 block diagram of interrupt contro l operation ........................................................... 72 figure 5.4 flowchart of procedure up to inte rrupt acceptance in interr upt control mode 0....... 75 figure 5.5 state transition in interrupt control mode 1 .............................................................. 76 figure 5.6 flowchart of procedure up to inte rrupt acceptance in interrupt control mode 1..... 78 figure 5.7 interrupt exception handling ...................................................................................... 79 figure 5.8 conflict between inte rrupt generation and disabling................................................. 81 section 6 bus controller (bsc) figure 6.1 block diag ram of bus co ntroller................................................................................ 84 figure 6.2 cs and address assertion period extension (example of 3-state acce ss space and r dnn = 0)..................................................... 89
rev. 2.00, 03/04, page xxii of xxxii figure 6.3 read strobe negation ti ming (example of 3- state access space) ............................ 93 figure 6.4 ras signal assertion timing (2-state column address out put cycle, fu ll access)................................................. 97 figure 6.5 area divisions.................................................................................................... ....... 102 figure 6.6 address format .................................................................................................... ..... 103 figure 6.7 address map ....................................................................................................... ...... 105 figure 6.8 csn signal output timing (n = 3 to 0) ..................................................................... 108 figure 6.9 access sizes and data a lignment control (8-b it access sp ace) ............................. 109 figure 6.10 access sizes and data a lignment control (16- bit access space) .......................... 110 figure 6.11 bus timing for 8-bit, 2-state access space ........................................................... 111 figure 6.12 bus timing for 8-bit, 3-state access space ........................................................... 112 figure 6.13 bus timing for 16-bit, 2-stat e access space (even address byte access)........... 113 figure 6.14 bus timing for 16-bit, 2-stat e access space (odd address byte access)............ 114 figure 6.15 bus timing for 16-bit, 2-state access space (word access) ................................ 115 figure 6.16 bus timing for 16-bit, 3-stat e access space (even address byte access)........... 116 figure 6.17 bus timing for 16-bit, 3-stat e access space (odd address byte access)............ 117 figure 6.18 bus timing for 16-bit, 3-state access space (word access) ................................ 118 figure 6.19 example of wa it state insertion timing................................................................. 119 figure 6.20 example of read strobe timing ............................................................................. 120 figure 6.21 example of timing when chip select assertion period is extended ..................... 121 figure 6.22 dram basic access timing (rast = 0, cast = 0)............................................ 124 figure 6.23 example of access timing with 3-state column address output cycle (rast = 0).............................................................................................................. 125 figure 6.24 example of access timing when ras signal goes low from beginning of t r state (cast = 0) ................................................................................................ 126 figure 6.25 example of timing with one row address output hold state (rast = 0, cast = 0)........................................................................................... 127 figure 6.26 example of timing with two-st ate precharge cycle (rast = 0, cast = 0)....... 128 figure 6.27 example of wait state insertio n timing (2-state column address output) .......... 129 figure 6.28 example of wait state insertio n timing (3-state column address output) .......... 130 figure 6.29 2-cas control timing (write access to even address: rast = 0, cast = 0) ... 131 figure 6.30 example of 2-cas dram connection .................................................................. 132 figure 6.31 operation timing in fast page mode (rast = 0, cast = 0) ............................... 133 figure 6.32 operation timing in fast page mode (rast = 0, cast = 1) ............................... 133 figure 6.33 example of operation timing in ras down mode (rast = 0, cast = 0)......... 135 figure 6.34 example of idle cycle insertio n when ras down mode cannot be continued..... 135 figure 6.35 example of operation timing in ras up mode (rast = 0, cast = 0).............. 136 figure 6.36 rtcnt operation.................................................................................................. .137 figure 6.37 compare match timing .......................................................................................... 138 figure 6.38 cbr refresh timing............................................................................................... 138 figure 6.39 cbr refresh timing (rcw1 = 0, rcw0 = 1, rlw1 = 0, rlw0 = 0)................. 138 figure 6.40 se lf-refresh timing .............................................................................................. .. 139
rev. 2.00, 03/04, page xxiii of xxxii figure 6.41 example of timing when precharge time after self-refreshing is extended by 2 stat es................................................................................................................ 140 figure 6.42 example of dack output timing when dds = 1 (rast = 0, cast = 0) .......... 141 figure 6.43 example of dack output timing when dds = 0 (rast = 0, cast = 1) .......... 142 figure 6.44 example of idle cycle operat ion (consecutive reads in different areas) ............ 143 figure 6.45 example of idle cycl e operation (write after read) .............................................. 144 figure 6.46 example of idle cy cle operation (read after write) .............................................. 145 figure 6.47 relationship between chip select ( cs ) and read ( rd ).......................................... 145 figure 6.48 example of dram full a ccess after external r ead (cast = 0) .......................... 146 figure 6.49 example of idle cy cle operation in ras down mode (consecutive reads in different areas) (idle1 = 0, idle0 = 1, idlc1 = 0, idlc0 = 1, rast = 0, and cast = 0)........ 147 figure 6.50 example of timing when write data buffer fu nction is used .............................. 150 section 7 dma controller (dmac) figure 7.1 block diagram of dmac ......................................................................................... 155 figure 7.2 example of timi ng in dual address mode............................................................... 173 figure 7.3 data flow in single addr ess mode........................................................................... 174 figure 7.4 example of timing in single address mode ............................................................ 175 figure 7.5 example of timi ng in cycle st eal mode .................................................................. 177 figure 7.6 examples of timing in bu rst mode .......................................................................... 178 figure 7.7 examples of timing in normal transfer mode ........................................................ 178 figure 7.8 example of timing in block transfer mode ............................................................ 179 figure 7.9 example of repeat area function operation............................................................ 180 figure 7.10 example of repeat area f unction operation in block transfer mode .................. 181 figure 7.11 dmtcr update operations in normal transfer mode and block transfer mode............................................................................................... 184 figure 7.12 procedure for changing re gister settings in op erating channel ........................... 185 figure 7.13 example of channel priority timing ...................................................................... 187 figure 7.14 examples of channel priority timing..................................................................... 188 figure 7.15 example of normal transf er mode (cycle steal mode) transfer .......................... 189 figure 7.16 example of normal tran sfer mode (burst mode) transfer.................................... 190 figure 7.17 example of normal transfer mode (cycle steal mode) transfer (transfer sour ce: usb) ........................................................................................... 190 figure 7.18 example of normal transfer mode (cycle steal mode) transfer (transfer destina tion: usb).................................................................................... 191 figure 7.19 example of block transfer mode (cycle steal mode) transfer............................. 191 figure 7.20 example of normal mode transfer activated by dreq pin falling edge............ 192 figure 7.21 example of block transfer mode transfer activated by dreq pin falling edge............................................................................................................. 193 figure 7.22 example of normal mode transfer activated by dreq pin low level............... 194 figure 7.23 example of block transfer mode transfer activated by dreq pin low level ... 195 figure 7.24 example of single a ddress mode (byte r ead) transfer ........................................ 196
rev. 2.00, 03/04, page xxiv of xxxii figure 7.25 example of single a ddress mode (word read) transfer....................................... 196 figure 7.26 example of single addr ess mode (longword read) transfer ............................... 197 figure 7.27 example of single a ddress mode (byte wr ite) transfer ....................................... 197 figure 7.28 example of single a ddress mode (word write) transfer...................................... 198 figure 7.29 example of single addr ess mode (longword write) transfer .............................. 198 figure 7.30 example of single a ddress mode transfer activated by dreq pin falling edge ............................................................................................................ 199 figure 7.31 example of single a ddress mode transfer activated by dreq pin low level ............................................................................................................... 200 figure 7.32 auto request/cycle steal mode/normal transfer mode (no contention/dual address mode)...................................................................... 201 figure 7.33 auto request/cycle steal mode/normal transfer mode (cpu cycles/single address mode) ....................................................................... 202 figure 7.34 auto request/cycle steal mode/normal transfer mode (contention with another cha nnel/single addre ss mode)..................................... 202 figure 7.35 auto request/burst mode/normal transfer mode (cpu cycles/dual ad dress mode).......................................................................... 203 figure 7.36 auto request/burst mode/normal transfer mode (cpu cycles/single address mode) ....................................................................... 203 figure 7.37 auto request/burst mode/normal transfer mode (contention with another cha nnel/single addre ss mode)..................................... 204 figure 7.38 external request/cycle steal mode/normal transfer mode (no contention/dual address mo de/low level sensing)...................................... 205 figure 7.39 external request/cycle steal mode/normal transfer mode (cpu cycles/single address m ode/low level sensing) ....................................... 205 figure 7.40 external request/cycle steal mode/normal transfer mode (no contention/single address mo de/falling edge sensing) ................................ 206 figure 7.41 external request/cycle steal mode/normal transfer mode (contention with another channel/dual address mode/low level sensing) ....... 206 figure 7.42 external request/cycle steal mode/block transfer mode (no contention/dual address mo de/low level sensing)...................................... 208 figure 7.43 external request/cycle steal mode/block transfer mode (no contention/single address mo de/falling edge sensing) ................................ 209 figure 7.44 external request/cycle steal mode/block transfer mode (cpu cycles/single address m ode/low level sensing) ....................................... 210 figure 7.45 external request/cycle steal mode/block transfer mode (contention with another channel/dual address mode/low level sensing) ....... 211 figure 7.46 transfer end interrupt logic................................................................................... 21 4 figure 7.47 example of procedure for restarting transfer on channel in which transfer end interrupt occurred ................................................................................................... 215
rev. 2.00, 03/04, page xxv of xxxii section 9 8-bit timer (tmr) figure 9.1 block diagram of 8-bit time r module..................................................................... 264 figure 9.2 example of pulse output........................................................................................... 270 figure 9.3 count timing fo r internal clock input...................................................................... 271 figure 9.4 count timing fo r external cloc k input .................................................................... 271 figure 9.5 timi ng of cmf setting ............................................................................................. 272 figure 9.6 timing of timer output ............................................................................................ 272 figure 9.7 timing of compare match clear............................................................................... 273 figure 9.8 timing of clear ance by external reset..................................................................... 273 figure 9.9 timi ng of ovf setting............................................................................................. .274 figure 9.10 contention betw een tcnt write and clear ........................................................... 276 figure 9.11 contention between tcnt write and increment.................................................... 277 figure 9.12 contention between tcor write and co mpare matc h.......................................... 278 section 10 watchdog timer (wdt) figure 10.1 block diagram of wdt .......................................................................................... 283 figure 10.2 watchdog timer mode (rst/ nmi = 1) operation................................................. 286 figure 10.3 interval timer mode operation............................................................................... 287 figure 10.4 ov f flag set timing .............................................................................................. 287 figure 10.5 outp ut timing of ovf............................................................................................ 2 88 figure 10.6 writing to tcnt and tcsr ................................................................................... 289 figure 10.7 conflict between tcnt write and increment ........................................................ 290 section 11 serial communication interface for boot mode (sci) figure 11.1 bloc k diagram of sci............................................................................................. 292 figure 11.2 data format in asynchronous communication (example with 8-bit data, pa rity, two stop bits) .................................................. 304 figure 11.3 receive data sampli ng timing in asynch ronous mode ........................................ 306 figure 11.4 sample sci initialization fl owchart ....................................................................... 307 figure 11.5 example of operation in transmission in asynchronous mode (example with 8-bit data, parity, one st op bit) .................................................... 308 figure 11.6 sample serial transmission flowchart ................................................................... 309 figure 11.7 example of sci operation in reception (example with 8-bit data, parity, one st op bit) .................................................... 310 figure 11.8 sample serial reception data flow chart (1) .......................................................... 312 figure 11.8 sample serial reception data flow chart (2) .......................................................... 313 figure 11.9 sample flowchart for mo de transition during transmission................................. 316 figure 11.10 sample flowchart for mode transition duri ng receptio n .................................... 317 section 12 universal serial bus 2 (usb2) figure 12.1 block diagram of usb2 ......................................................................................... 320 figure 12.2 usb cable connection ........................................................................................... 34 1 figure 12.3 usb ca ble disconn ection....................................................................................... 342 figure 12.4 control transf er stage confi guration ..................................................................... 343
rev. 2.00, 03/04, page xxvi of xxxii figure 12.5 set up stage operation ............................................................................................ .344 figure 12.6 data stage operation (con trol-in) .......................................................................... 345 figure 12.7 data stage operation (control-out) ....................................................................... 346 figure 12.8 status stag e operation (cont rol-in)........................................................................ 347 figure 12.9 status stag e operation (cont rol-out) ..................................................................... 348 figure 12.10 ep1 bulk-out transfer operation......................................................................... 350 figure 12.11 ep2 bulk-i n transfer operation ........................................................................... 352 figure 12.12 ep3 interrupt- in transfer operation ..................................................................... 353 figure 12.13 forcible stall by firmware.................................................................................... 35 6 figure 12.14 automatic sta ll by usb functi on module............................................................ 357 figure 12.15 pkte2 operation for ep2..................................................................................... 359 figure 12.16 enter/recover sequ ence of usb susp end state ................................................... 360 figure 12.17 enter/recover sequence of us b suspend state and software standby mode..... 362 figure 12.18 connection exam ple of external circuit............................................................... 367 figure 12.19 bus reset following completion of firs t bus reset ............................................ 368 figure 12.20 bus re set detection flow ..................................................................................... 369 section 14 flash memory (0.18- m f-ztat version) figure 14.1 block diag ram of flash memory............................................................................ 374 figure 14.2 mode tran sition of flas h memory.......................................................................... 375 figure 14.3 flash me mory configur ation .................................................................................. 377 figure 14.4 block divi sion of user mat.................................................................................. 378 figure 14.5 overview of user procedure program .................................................................... 379 figure 14.6 system conf iguration in b oot mode....................................................................... 402 figure 14.7 automatic-bit-rate adjustment operation of sci ................................................. 402 figure 14.8 overview of boot mode state trans ition diagram................................................. 404 figure 14.9 programming/ erasing overview flow.................................................................... 405 figure 14.10 ram map when pr ogramming/erasing is executed ........................................... 406 figure 14.11 progr amming procedure........................................................................................ 407 figure 14.12 er asing procedure ............................................................................................... .. 412 figure 14.13 repeating procedur e of erasing and programming............................................... 414 figure 14.14 procedure for programmi ng user mat in user boot mode ................................ 416 figure 14.15 procedure for erasin g user mat in user boot mode .......................................... 417 figure 14.16 transitions to error-protectio n state..................................................................... 430 figure 14.17 switching between th e user mat and user boot mat ...................................... 431 figure 14.18 flowchart for flas h memory emulati on in ram ................................................. 432 figure 14.19 example of ram overlap operation (256-kbyte flash memory)........................ 433 figure 14.20 memory ma p in programmer mode...................................................................... 434 figure 14.21 b oot program states............................................................................................. .436 figure 14.22 bit-rate -adjustment sequence ............................................................................. 437 figure 14.23 communica tion protocol format .......................................................................... 438 figure 14.24 new bit-ra te selection sequence......................................................................... 448 figure 14.25 progr amming sequence......................................................................................... 451
rev. 2.00, 03/04, page xxvii of xxxii figure 14.26 erasure sequence ................................................................................................ .. 454 section 15 clock pulse generator figure 15.1 block diagram of clock pulse generator ............................................................... 463 figure 15.2 connection of cr ystal resonator (example)........................................................... 464 figure 15.3 crystal resona tor equivalent circuit ...................................................................... 464 figure 15.4 external clock input (e xamples) ............................................................................ 465 figure 15.5 external clock input timing................................................................................... 465 figure 15.6 timing of external cl ock output stabiliza tion delay time ................................... 466 figure 15.7 note on board de sign for oscilla tion circuit ......................................................... 467 section 16 power-down modes figure 16.1 mode transitions................................................................................................. .... 471 figure 16.2 software stand by mode applicati on example ....................................................... 476 figure 16.3 hardware standby mode timing ............................................................................ 477 section 18 electrical characteristics figure 18.1 sample of dalingt on transistor dr ive circuit......................................................... 500 figure 18.2 outp ut load circuit.............................................................................................. ... 501 figure 18.3 system clock timing .............................................................................................. 502 figure 18.4 oscillation st abilization ti ming (1) ........................................................................ 502 figure 18.5 oscillation st abilization ti ming (2) ........................................................................ 502 figure 18.6 re set input timing............................................................................................... ... 503 figure 18.7 interrupt input timing........................................................................................... .. 503 figure 18.8 basic bus ti ming: two-stat e access ..................................................................... 506 figure 18.9 basic bus ti ming: three-stat e access ................................................................... 507 figure 18.10 basic bus timing: two-state access ( cs assertion period extended) ............... 508 figure 18.11 basic bus timing: three-state access ( cs assertion period extended) ............. 509 figure 18.12 dram access timing: two-stat e access ........................................................... 510 figure 18.13 dram access timi ng: two-state bu rst access ................................................. 511 figure 18.14 dram access timing: three-state access (rast = 1) ..................................... 512 figure 18.15 dram access timi ng: three-state bu rst access ............................................... 513 figure 18.16 cas-before -ras refresh timing......................................................................... 514 figure 18.17 cas-before-ras refresh timing (with wait cy cle insertion) ........................... 514 figure 18.18 self-refresh timing (ret urn from software standby mode: rast = 0) ............. 514 figure 18.19 self-refresh timing (ret urn from software standby mode: rast = 1) ............. 515 figure 18.20 dmac single address transfer timing: tw o-state access................................ 516 figure 18.21 dmac single address tr ansfer timing: thr ee-state access.............................. 517 figure 18.22 dmac, tend output timing.............................................................................. 517 figure 18.23 dmac, dreq input ti ming ................................................................................ 518 figure 18.24 i/o port input/output timing................................................................................ 519 figure 18.25 8-bit ti mer output timing ................................................................................... 519 figure 18.26 8-bit time r clock input timing ........................................................................... 519 figure 18.27 8-bit time r reset input timing ............................................................................ 519
rev. 2.00, 03/04, page xxviii of xxxii figure 18.28 usb2 input/output timing.................................................................................... 520 figure 18.29 vcl capac itor connection method...................................................................... 522 appendix figure c.1 package di mensions (tfp -100b) ............................................................................ 526
rev. 2.00, 03/04, page xxix of xxxii tables section 1 overview table 1.1 pin arrangements in each mode............................................................................. 4 table 1.2 pin functions........................................................................................................... 8 section 2 cpu table 2.1 instruction cla ssification....................................................................................... 29 table 2.2 operation notation ................................................................................................ 30 table 2.3 data transfer instructions ..................................................................................... 31 table 2.4 arithmetic operations instructions (1).................................................................. 32 table 2.4 arithmetic operations instructions (2).................................................................. 33 table 2.5 logic operations instructions ............................................................................... 34 table 2.6 shift instructions ................................................................................................... 34 table 2.7 bit manipulation inst ructions (1) .......................................................................... 35 table 2.7 bit manipulation inst ructions (2) .......................................................................... 36 table 2.8 branch instructions................................................................................................ 37 table 2.9 system control instructions .................................................................................. 38 table 2.10 block data transfer instructions........................................................................... 39 table 2.11 addressing modes................................................................................................. 40 table 2.12 absolute address access ranges ......................................................................... 42 table 2.13 effective address ca lculation (1) ......................................................................... 44 table 2.13 effective address ca lculation (2) ......................................................................... 45 section 3 mcu operating modes table 3.1 mcu operating mode selection........................................................................... 49 table 3.2 pin functions in operating mode 2....................................................................... 52 section 4 exception handling table 4.1 exception types and priority ................................................................................ 55 table 4.2 exception handling vector table ......................................................................... 56 table 4.3 status of ccr after trap inst ruction exception handling .................................... 59 section 5 interrupt controller table 5.1 pin configuration .................................................................................................. 64 table 5.2 correspondence between inte rrupt source and icr ............................................. 65 table 5.3 interrupt sources, vector addre sses, and interrupt priorities ............................... 70 table 5.4 interrupt control modes........................................................................................ 72 table 5.5 interrupts acceptable in each interrupt control mode ......................................... 73 table 5.6 operations and control signal functions in each interrupt control mode .......... 73 table 5.7 interrupt response times...................................................................................... 80 table 5.8 number of states in interrupt handling routine execution status....................... 80
rev. 2.00, 03/04, page xxx of xxxii section 6 bus controller (bsc) table 6.1 pin configuration .................................................................................................. 85 table 6.2 address ma p ....................................................................................................... 104 table 6.3 bus specifications for each ar ea (basic bus interface) ..................................... 106 table 6.4 data buses used and valid stro bes .................................................................... 110 table 6.5 relation between settings of bits mxc2 to mxc0 and address multip lexing ......................................................................................... 122 table 6.6 dram interface pins.......................................................................................... 123 table 6.7 idle cycles in mixed accesses to normal space and dram space.................. 148 table 6.8 pin states in id le cycle ....................................................................................... 149 section 7 dma controller (dmac) table 7.1 pin configuration ................................................................................................ 156 table 7.2 dmac transfer modes ...................................................................................... 171 table 7.3 dmac channel priority ..................................................................................... 186 table 7.4 interrupt sources and priority or der ................................................................... 213 section 8 i/o ports table 8.1 port functions ..................................................................................................... 220 section 9 8-bit timer (tmr) table 9.1 pin configuration ................................................................................................ 265 table 9.2 clock input to tcnt an d count condition ........................................................ 268 table 9.3 8-bit timer interr upt sources ............................................................................. 275 table 9.4 timer output priorities ....................................................................................... 279 table 9.5 switching of internal cloc k and tcnt operation ............................................. 280 section 10 watchdog timer (wdt) table 10.1 wdt interrupt source......................................................................................... 288 section 11 serial communication interface for boot mode (sci) table 11.1 pin configuration ................................................................................................ 292 table 11.2 relationships between n setti ng in brr and bit rate b ................................... 300 table 11.3 brr settings for various bit rates (asynchronous mode) (1).......................... 301 table 11.3 brr settings for various bit rates (asynchronous mode) (2).......................... 302 table 11.4 maximum bit rate for each fre quency (asynchronous mode)......................... 303 table 11.5 serial transfer formats (asynchronous mode) .................................................. 305 table 11.6 ssr status flags and recei ve data ha ndling..................................................... 311 table 11.7 sci interrupt sources .......................................................................................... 314 section 12 universal serial bus 2 (usb2) table 12.1 input/output signals ........................................................................................... 321 table 12.2 request decoding by firmware .......................................................................... 354 table 12.3 tree configuration .............................................................................................. 358 table 12.4 fifo size in each transfer mode ...................................................................... 366
rev. 2.00, 03/04, page xxxi of xxxii section 14 flash memory (0.18- m f-ztat version) table 14.1 comparison of prog ramming modes .................................................................. 376 table 14.2 pin configuration ................................................................................................ 381 table 14.3 register/parameter an d target mode .................................................................. 382 table 14.4 flash memory area divisions............................................................................. 391 table 14.5 parameters and ta rget modes ............................................................................. 392 table 14.6 setting on-board prog ramming mode................................................................ 401 table 14.7 system clock frequency for automatic-b it-rate adjustment by this lsi ....... 403 table 14.8 executable mat ................................................................................................. 419 table 14.9 (1) useable area for programming in user program mode ..................................... 420 table 14.9 (2) useable area for erasure in user program mode ............................................... 422 table 14.9 (3) useable area for programming in user boot mode ........................................... 424 table 14.9 (4) useable area for erasure in user boot mode ..................................................... 426 table 14.10 hardware protection............................................................................................ 428 table 14.11 software protection ............................................................................................. 429 table 14.12 inquiry and selec tion commands ....................................................................... 439 table 14.13 programming/erasin g command ........................................................................ 450 table 14.14 status co de.......................................................................................................... 459 table 14.15 error code ........................................................................................................... 460 section 15 clock pulse generator table 15.1 damping resistance value.................................................................................. 464 table 15.2 crystal resonator ch aracteristic s........................................................................ 464 table 15.3 external clock in put conditi ons ......................................................................... 465 table 15.4 external clock output st abilization dela y time ................................................ 466 section 16 power-down modes table 16.1 operating modes and intern al states of lsi ....................................................... 470 table 16.2 operating frequency an d standby time ............................................................. 475 section 18 electrical characteristics table 18.1 absolute maximum ratings................................................................................ 497 table 18.2 dc characteris tics (1) ......................................................................................... 498 table 18.3 dc characteris tics (2) ......................................................................................... 499 table 18.4 permissible output currents................................................................................ 500 table 18.5 clock timing....................................................................................................... 501 table 18.6 control signal timing......................................................................................... 503 table 18.7 bus timing (1) .................................................................................................... 504 table 18.8 bus timing (2) .................................................................................................... 505 table 18.9 dmac timing .................................................................................................... 515 table 18.10 timing of on-chip peripheral modules.............................................................. 518 table 18.11 flash memory char acteristic s............................................................................. 521
rev. 2.00, 03/04, page xxxii of xxxii
rev. 2.00, 03/04, page 1 of 534 section 1 overview 1.1 features ? ? ? ? ? ? ? ? ? ? ? ? rom type model rom ram remarks flash memory version HD64F2170 256 kbytes 32 kbytes ? ? ? package (code) body size pin pitch remarks tqfp-100 tfp-100b 14.0 14.0 mm 0.5 mm ?
rev. 2.00, 03/04, page 2 of 534 1.2 internal block diagram figure 1.1 shows the internal block diagram. h8s/2000 cpu pll ram dmac wdt sci p97/ p96/ p95/ p94/ p93/ p92/ / p91/ p90/ pa3/a19/ pa2/a18/ pa1/a17/ /( ) pa0/a16/( ) md1 fwe extal xtal nmi huditck rxd0/huditdi txd0/huditdo hudims p87/d15 p86/d14 p85/d13 p84/d12 p83/d11 p82/d10 p81/d9 p80/d8 p17/usd15 p16/usd14 p15/usd13 p14/usd12 p13/usd11 p12/usd10 p11/usd9 p10/usd8 p27/usd7/ p26/usd6/ p25/usd5/ p24/usd4/ p23/usd3/ p22/usd2/ p21/usd1/ p20/usd0/ p37/usopm1 p36/usopm0 p35/( )/usvbus p34/( )/ustxv p33/uslsta1 p32/uslsta0 p31/usclk p30/uswdvld p47/usxcvrs p46/ustxrdy p45/ustsel p44/ p43/usrxv p42/usrxerr p41/usrxact p40/ p77/a7/ p76/a6/ p75/a5/ p74/a4/ p73/a3/ p72/a2/ p71/a1/ p70/a0/ p67/a15 p66/a14/tmo1 p65/a13/tmri1 p64/a12/tmci1 p63/a11 p62/a10/tmo0 p61/a9/tmri0 p60/a8/tmci0 vcl vcc vcc vcc vcc vss vss vss vss vss p57/d7/( )/ p56/d6/( )/ p55/d5/ p54/d4/ p53/d3/( )/ p52/d2/( )/ p51/d1/ p50/d0/ clock pulse generator interrupt controller bus controller usb2.0 interface rom (flash memory) 8-bit timer port 1 port 2 port 3 port 4 port 7 port 6 port 5 port 8 port 9 port a 32-bit internal data bus 32-bit internal address bus 32-bit internal address bus 16-bit internal address bus 16-bit internal data bus 32-bit internal data bus figure 1.1 internal block diagram
rev. 2.00, 03/04, page 3 of 534 1.3 pin description 1.3.1 pin arrangement figure 1.2 shows the pin arrangement. p72/a2/ p71/a1/ p70/a0/ p87/d15 p86/d14 p85/d13 p84/d12 p83/d11 p82/d10 p81/d9 p80/d8 vcc fwe vss p57/d7/( )/ p56/d6/( )/ p55/d5/ p54/d4/ p53/d3/( )/ p52/d2/( )/ p51/d1/ p50/d0/ pa0/a16/( ) pa1/a17/ /( ) p17/usd15 p16/usd14 p15/usd13 p14/usd12 p13/usd11 p12/usd10 p11/usd9 p10/usd8 vcc huditck vss huditdi/rxd0 p27/usd7/ p26/usd6/ p25/usd5/ p24/usd4/ p23/usd3/ p22/usd2/ p21/usd1/ p20/usd0/ p37/usopm1 p36/usopm0 p35/( )/usvbus p34/( )/ustxv p33/uslsta1 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 pa2/a18/ pa3/a19/ md1 nc nmi vss vcl vss extal xtal vcc p97/ p96/ p95/ p94/ p93/ p92/ / p91/ p90/ p30/uswdvld p31/usclk p32/uslsta0 p73/a3/ p74/a4/ p75/a5/ p76/a6/ p77/a7/ vss huditdo/txd0 vcc huditms p60/a8/tmci0 p61/a9/tmri0 p62/a10/tmo0 p63/a11 p64/a12/tmci1 p65/a13/tmri1 p66/a14/tmo1 p67/a15 p47/usxcvrs p46/ustxrdy p45/ustsel p44/ p43/usrxv p42/usrxerr p41/usrxact p40/ tfp-100b (top view) figure 1.2 pin arrangement (tfp-100b)
rev. 2.00, 03/04, page 4 of 534 1.3.2 pin arrangements in each mode table 1.1 lists the pin arrangements in each mode. table 1.1 pin arrangements in each mode pin no. pin name tfp- extended mode single-chip mode 100b (expe = 1) (expe = 0) flash memory programmer mode 1 pa2/a18/ ucas pa2 nc 2 pa3/a19/ cs3 pa3 nc 3 md2 md2 vss 4 md1 md1 vss 5 nc nc nc 6 nmi nmi nc 7 vss vss vss 8 stby stby vcc 9 vcl vcl vcl 10 res res res 11 vss vss vss 12 extal extal extal 13 xtal xtal xtal 14 vcc vcc vcc 15 p97/ p97/ nc 16 p96/ as p96 nc 17 p95/ rd p95 nc 18 p94/ hwr p94 nc 19 p93/ lwr p93 nc 20 p92/ cs2 / ras p92 nc 21 p91/ cs1 p91 nc 22 p90/ cs0 p90 nc 23 p30/uswdvld p30/uswdvld nc 24 p31/usclk p31/usclk nc 25 p32/uslsta0 p32/uslsta0 nc 26 p33/uslsta1 p33/uslsta1 nc 27 p34/( irq4 )/ustxv p34/( irq4 )/ustxv nc
rev. 2.00, 03/04, page 5 of 534 pin no. pin name tfp- extended mode single-chip mode 100b (expe = 1) (expe = 0) flash memory programmer mode 28 p35/( irq5 )/usvbus p35/( irq5 )/usvbus nc 29 p36/usopm0 p36/usopm0 nc 30 p37/usopm1 p37/usopm1 nc 31 p20/usd0/ dreq0 p20/usd0/ dreq0 nc 32 p21/usd1/ tend0 p21/usd1/ tend0 nc 33 p22/usd2/ dack0 p22/usd2/ dack0 nc 34 p23/usd3/ drak0 p23/usd3/ drak0 nc 35 p24/usd4/ dreq1 p24/usd4/ dreq1 nc 36 p25/usd5/ tend1 p25/usd5/ tend1 nc 37 p26/usd6/ dack1 p26/usd6/ dack1 nc 38 p27/usd7/ drak1 p27/usd7/ drak1 nc 39 huditdi/rxd0 huditdi/rxd0 nc 40 vss vss vss 41 huditck huditck nc 42 vcc vcc vcc 43 p10/usd8 p10/usd8 nc 44 p11/usd9 p11/usd9 nc 45 p12/usd10 p12/usd10 nc 46 p13/usd11 p13/usd11 nc 47 p14/usd12 p14/usd12 nc 48 p15/usd13 p15/usd13 nc 49 p16/usd14 p16/usd14 nc 50 p17/usd15 p17/usd15 nc 51 p40/ usrst p40/ usrst nc 52 p41/usrxact p41/usrxact nc 53 p42/usrxerr p42/usrxerr nc 54 p43/usrxv p43/usrxv nc 55 p44/ ussusp p44/ ussusp nc 56 p45/ustsel p45/ustsel nc 57 p46/ustxrdy p46/ustxrdy nc 58 p47/usxcvrs p47/usxcvrs nc 59 p67/a15 p67 nc
rev. 2.00, 03/04, page 6 of 534 pin no. pin name tfp- extended mode single-chip mode 100b (expe = 1) (expe = 0) flash memory programmer mode 60 p66/a14/tmo1 p66/tmo1 nc 61 p65/a13/tmri1 p65/tmri1 nc 62 p64/a12/tmci1 p64/tmci1 nc 63 p63/a11 p63 nc 64 p62/a10/tmo0 p62/tmo0 nc 65 p61/a9/tmri0 p61/tmri0 nc 66 p60/a8/tmci0 p60/tmci0 nc 67 huditms huditms nc 68 vcc vcc vcc 69 huditdo/txd0 huditdo/txd0 nc 70 vss vss vss 71 p77/a7/ irq7 p77/ irq7 nc 72 p76/a6/ irq6 p76/ irq6 nc 73 p75/a5/ irq5 p75/ irq5 nc 74 p74/a4/ irq4 p74/ irq4 nc 75 p73/a3/ irq3 p73/ irq3 nc 76 p72/a2/ irq2 p72/ irq2 nc 77 p71/a1/ irq1 p71/ irq1 nc 78 p70/a0/ irq0 p70/ irq0 nc 79 p87/d15 p87 nc 80 p86/d14 p86 nc 81 p85/d13 p85 nc 82 p84/d12 p84 nc 83 p83/d11 p83 nc 84 p82/d10 p82 nc 85 p81/d9 p81 nc 86 p80/d8 p80 nc 87 vcc vcc vcc 88 fwe fwe fwe 89 huditrst huditrst nc 90 vss vss vss 91 p57/d7/( irq7 )/mssrac/ drak3 p57/( irq7 )/mssrac/ drak3 nc
rev. 2.00, 03/04, page 7 of 534 pin no. pin name tfp- extended mode single-chip mode 100b (expe = 1) (expe = 0) flash memory programmer mode 92 p56/d6/( irq6 )/ dack3 p56/( irq6 )/ dack3 nc 93 p55/d5/msbs/ tend3 p55/msbs/ tend3 nc 94 p54/d4/msdio3/ dreq3 p54/msdio3/ dreq3 nc 95 p53/d3/( irq3 )/msdio2/ drak2 p53/( irq3 )/msdio2/ drak2 nc 96 p52/d2/( irq2 )/msdio1/ dack2 p52/( irq2 )/msdio1/ dack2 nc 97 p51/d1/msdio0/ tend2 p51/msdio0/ tend2 nc 98 p50/d0/msclk/ dreq2 p50/msclk/ dreq2 nc 99 pa0/a16/( irq0 ) pa0/( irq0 ) nc 100 pa1/a17/ lcas /( irq1 ) pa1/ lcas /( irq1 ) nc
rev. 2.00, 03/04, page 8 of 534 1.3.3 pin functions table 1.2 lists the pin functions. table 1.2 pin functions type symbol pin no. i/o function power v cc 14, 42, 68, 87 input for connection to the power supply. v cc pins should be connected to the system power supply. v ss 7, 11, 40, 70, 90 input for connection to ground. v ss pins should be connected to the system power supply (0 v). v cl 9 output the v cl is an external capacity pin for internal step- down power. connect this pin to v ss through the external capacitor to stabilize the internal step-down power. clock xtal 13 input for connection to a crystal resonator. see section 15, clock pulse generator for typical connection diagrams for a crystal resonator and external clock input. extal 12 input for connection to a crystal resonator. the extal pin can also input an external clock. see section 15, clock pulse generator for typical connection diagrams for a crystal resonator and external clock input. 15 output supplies the system clock to external devices. operating mode control md2 md1 3 4 input these pins set the operating mode. these pins should not be changed while the mcu is operating. system control res 10 input reset pin. when this pi n is driven low, the chip is reset. stby 8 input when this pin is driv en low, a transition is made to hardware standby mode. fwe 88 input this pin is only for the flash memory. this pin is available only in the flash memory version.
rev. 2.00, 03/04, page 9 of 534 type symbol pin no. i/o function interrupt signals nmi 6 input nonmaskable interrupt request pin. fix high when not used. irq7 to irq0 71 to 78 input these pins request a maskable interrupt. the irq sense port select register (issr) selects whether the signal is input from the irqn or ( irqn ). (n = 7 to 0) ( irq7 ) to ( irq0 ) 91, 92, 28, 27, 95, 96, 99, 100 input address bus a19 a18 a17 a16 a15 to a8 a7 to a0 2, 1, 100, 99, 59 to 66, 71 to 78 output these pins output an address. data bus d15 to d8, d7 to d0 79 to 86, 91 to 98 input/ output these pins constitute a bidirectional data bus. bus control cs3 2 output strobe signal indicating that area 3 is selected. cs2 / ras 20 output strobe signal indicating that area 2 is selected. row address strobe signal for the dram. cs1 21 output strobe signal indicating that area 1 is selected. cs0 22 output strobe signal indicating that area 0 is selected. as 16 output when this pin is low, it indicates that address output on the address bus is valid. rd 17 output when this pin is low, it indicates that the normal space is being read. hwr 18 output strobe signal indicating that normal space is to be written, and the upper half (d15 to d8) of the data bus is enabled. lwr 19 output strobe signal indicating that normal space is to be written, and the lower half (d7 to d0) of the data bus is enabled. ucas 1 output upper column address strobe signal for accessing the 16-bit dram space or column address strobe signal for accessing the 8-bit dram space. lcas 100 output lower column address strobe signal for accessing the 16-bit dram space.
rev. 2.00, 03/04, page 10 of 534 type symbol pin no. i/o function dma controller (dmac) dreq3 dreq2 dreq1 dreq0 94, 98, 35, 31 input these signals request dmac activation for channels 3 to 0. dack3 dack2 dack1 dack0 92 96 37 33 output dmac single address transfer acknowledge signals for channels 3 to 0. tend3 tend2 tend1 tend0 93, 97, 36, 32 output these signals indicate the end of dmac data transfer for channels 3 to 0. drak3 drak2 drak1 drak0 91, 95, 38, 34 output these signals notify dmac external request acknowledge and execution start for channels 3 to 0 to external devices. 8-bit timer (tmr) tmo1 tmo0 60, 64 output compare match output pins. tmci1 tmci0 62, 66 input external clock input pins to counters. tmri1 tmri0 61, 65 input counter reset input pins. txd0 69 output data output pin. serial communicati- on interface for boot mode (sci) rxd0 39 input data input pin. usclk 23 input usb clock. usvbus 28 input input pin for co nnection/disconnection detection of usb cable. uslsta0 25 input input signal pins from usb2.0 transceiver. uslsta1 26 input usrxact 52 input usrxerr 53 input usrxv 54 input ustxrdy 57 input uswdvld 23 input/ output usopm0 29 output output signal pins for usb2.0 transceiver. universal serial bus 2 (usb2) usopm1 30 output
rev. 2.00, 03/04, page 11 of 534 type symbol pin no. i/o function usrst 51 output output signal pins for usb2.0 transceiver. ustxv 27 output ussusp 55 output ustsel 56 output usxcvrs 58 output universal serial bus 2 (usb2) usd15 to usd8 usd7 to usd0 50 to 43, 38 to 31 input/ output data input/output. i/o ports p17 to p10 50 to 43 input/ output eight-bit input/output pins. p27 to p20 38 to 31 input/ output eight-bit input/output pins. p37 to p30 30 to 23 input/ output eight-bit input/output pins. p47 to p40 58 to 51 input/ output eight-bit input/output pins. p57 to p50 91 to 98 input/ output eight-bit input/output pins. p67 to p60 59 to 66 input/ output eight-bit input/output pins. p77 to p70 71 to 78 input/ output eight-bit input/output pins. p87 to p80 79 to 86 input/ output eight-bit input/output pins. p97 to p90 15 to 22 input/ output eight-bit input/output pins. pa3 pa2 pa1 pa0 2, 1, 100, 99 input/ output four-bit input/output pins.
rev. 2.00, 03/04, page 12 of 534
rev. 2.00, 03/04, page 13 of 534 section 2 cpu the h8s/2000 cpu is a high-speed central processing unit with an internal 32-bit architecture that is upward-compatible with the h8/300 and h8/300h cpus. the h8s/2000 cpu has sixteen 16-bit general registers, can address a 16-mbyte linear ad dress space, and is ideal for realtime control. this section describes the h8s/2000 cpu. the us able modes and address spaces differ depending on the product. for details on each product, refer to section 3, mcu operating modes. 2.1 features ? ? ? ? ? ?
rev. 2.00, 03/04, page 14 of 534 ? ? ? ? ? execution states instruction mnemonic h8s/2600 h8s/2000 mulxu mulxu.b rs, rd 3 12 mulxu.w rs, erd 4 20 mulxs mulxs.b rs, rd 4 13 mulxs.w rs, erd 5 21 in addition, there are differences in address sp ace, ccr and exr register functions, power-down modes, etc., depending on the model.
rev. 2.00, 03/04, page 15 of 534 2.1.2 differences from h8/300 cpu in comparison to the h8/300 cpu, the h8s/2000 cpu has the following enhancements. ? ? ? ? ? ? ? ?
rev. 2.00, 03/04, page 16 of 534 2.2 cpu operating modes the h8s/2000 cpu has two operating modes: normal and advanced. normal mode supports a maximum 64-kbyte address space. advanced mode supports a ma ximum 16-mbyte address space. the mode is selected by the lsi's mode pins. 2.2.1 normal mode the exception vector table and stack have the sa me structure as in th e h8/300 cpu in normal mode. ? ? ? ? ? ?
rev. 2.00, 03/04, page 17 of 534 h'0000 h'0001 h'0002 h'0003 h'0004 h'0005 h'0006 h'0007 h'0008 h'0009 h'000a h'000b reset exception vector (reserved for system use) (reserved for system use) exception vector 1 exception vector 2 exception vector table figure 2.1 exception vector table (normal mode) pc (16 bits) exr * 1 reserved * 1 , * 3 ccr ccr * 3 pc (16 bits) sp sp (sp * 2 1. when exr is not used, it is not stored on the stack. 2. sp when exr is not used. 3. lgnored when returning. notes: (b) exception handling (a) subroutine branch ) figure 2.2 stack structure in normal mode
rev. 2.00, 03/04, page 18 of 534 2.2.2 advanced mode ? ? ? ? h'00000000 h'00000003 h'00000004 h'0000000b h'0000000c h'00000010 h'00000008 h'00000007 reserved reserved reserved reset exception vector ( reserved for system use ) ( reserved for system use ) exception vector table exception vector 1 figure 2.3 exception vector table (advanced mode)
rev. 2.00, 03/04, page 19 of 534 the memory indirect addressing mode (@@aa:8) employed in the jmp and jsr instructions uses an 8-bit absolute address included in the instruction code to specify a memory operand that contains a branch address. in advanced mode, the operand is a 32-bit longword operand, providing a 32-bit branch address. the upper 8 bits of these 32 bits are a reserved area that is regarded as h'00. branch addresses can be stored in the area from h'00000000 to h'000000ff. note that the top area of th is range is also used for the exception vector table. ? pc (24 bits) exr * 1 reserved * 1 , * 3 ccr pc (24 bits) sp sp (sp * 2 reserved (a) subroutine branch (b) exception handling notes: 1. when exr is not used, it is not stored on the stack. 2. sp when exr is not used. 3. ignored when returning. ) figure 2.4 stack structure in advanced mode
rev. 2.00, 03/04, page 20 of 534 2.3 address space figure 2.5 shows a memory map of the h8s/2000 cpu. the h8s/2000 cpu provides linear access to a maximum 64-kbyte address space in normal mode, and a maximum 16-mbyte (architecturally 4-gbyte) addr ess space in advanced mode. the usable modes and address spaces differ dependin g on the product. for details on each prod uct, refer to section 3, mcu operating modes. h'0000 h'ffff note: for this lsi, normal mode is not available. h'00000000 h'ffffffff h'00ffffff 64 kbyte 16 mbyte not available in this lsi program area data area (b) advanced mode (a) normal mode * figure 2.5 memory map
rev. 2.00, 03/04, page 21 of 534 2.4 register configuration the h8s/2000 cpu has the internal registers shown in figure 2.6. there are two types of registers: general registers and control registers. control registers are a 24-bit program counter (pc), an 8-bit extended control register (exr), and an 8-bit condition code register (ccr). ti2i1i0 exr 76543210 pc 23 0 15 0 7 0 7 0 e0 e1 e2 e3 e4 e5 e6 e7 r0h r1h r2h r3h r4h r5h r6h r7h r0l r1l r2l r3l r4l r5l r6l r7l sp: pc: exr: t: i2 to i0: ccr: i: ui: stack pointer program counter extended control register trace bit interrupt mask bits * condition-code register interrupt mask bit user bit or interrupt mask bit half-carry flag user bit negative flag zero flag overflow flag carry flag er0 er1 er2 er3 er4 er5 er6 er7 (sp) iuihunzvc ccr 76543210 h: u: n: z: v: c: general registers (rn) and extended registers (en) control registers [legend] ---- note: for this lsi, the interrupt mask bit is not available. figure 2.6 cpu internal registers
rev. 2.00, 03/04, page 22 of 534 2.4.1 general registers the h8s/2000 cpu has eight 32-bit general registers. these general registers are all functionally alike and can be used as both address registers and data registers. when a general register is used as a data register, it can be accessed as a 32-bit, 16-bit, or 8-bit register. figure 2.7 illustrates the usage of the general registers. when the general registers are used as 32-bit registers or address registers, they are designated by the letters er (er0 to er7). when the general registers are used as 16-bit registers, the er registers are divided into 16-bit general registers designated by the letters e (e 0 to e7) and r (r0 to r7). these registers are functionally equivalent, providing a maximum sixteen 16-bit registers. the e registers (e0 to e7) are also referred to as extended registers. when the general registers are used as 8-bit registers, the r registers are divided into 8-bit general registers designated by the letters rh (r0h to r7h) and rl (r0l to r7l). these registers are functionally equivalent, providing a maximum sixteen 8-bit registers. the usage of each register can be selected independently. general register er7 has the function of the stack pointer (sp) in addition to its general-register function, and is used implicitly in exception handling and subroutine calls. figure 2.8 shows the stack. ? address registers 32-bit registers 16-bit registers 8-bit registers er registers (er0 to er7) e registers (extended registers) (e0 to e7) r registers (r0 to r7) rh registers (r0h to r7h) rl registers (r0l to r7l) figure 2.7 usage of general registers
rev. 2.00, 03/04, page 23 of 534 sp (er7) free area stack area figure 2.8 stack 2.4.2 program counter (pc) this 24-bit counter indicates the address of the ne xt instruction the cpu will execute. the length of all cpu instructions is 2 bytes (one word), so the least significant pc bit is ignored. (when an instruction is fetched for read, the leas t significant pc bit is regarded as 0.) 2.4.3 extended control register (exr) exr is an 8-bit register that can be operated by the ldc, stc, andc, orc, and xorc instructions. when an instruction other than st c is executed, all interrupts including nmi are masked in three states after the instruction is completed. bit bit name initial value r/w description 7 t 0 r/w trace bit when this bit is set to 1, trace exception processing starts every when an instruction is executed. when this bit is cleared to 0, instructions are consecutively executed. 6 to3 ? all1 ? reserved these bits are always read as 1. 2 to 0 i2 i1 i0 1 1 1 r/w r/w r/w interrupt mask bits 2 to 0 specify interrupt request mask levels (0 to 7). in this lsi, these bits cannot be used as the interrupt mask level.
rev. 2.00, 03/04, page 24 of 534 2.4.4 condition-code register (ccr) this 8-bit register contains internal cpu status information, including an interrupt mask bit (i) and half-carry (h), negative (n), zero (z), overflow (v), and carry (c) flags. operations can be performed on the ccr bits by the ldc, stc, andc, orc, and xorc instructions. the n, z, v, and c flags are used as branching conditions for conditional branch (bcc) instructions. bit bit name initial value r/w description 7 i 1 r/w interrupt mask bit masks interrupts other than nmi when set to 1. nmi is accepted regardless of the i bit setting. the i bit is set to 1 at the start of an exception-handling sequence. for details, refer to section 5, interrupt controller. 6 ui undefined r/w user bit or interrupt mask bit can be written to and read from by software using the ldc, stc, andc, orc, and xorc instructions. 5 h undefined r/w half-carry flag when the add.b, addx.b, sub.b, subx.b, cmp.b or neg.b instruction is executed, this flag is set to 1 if there is a carry or borrow at bit 3, and cleared to 0 otherwise. when the add.w, sub.w, cmp.w, or neg.w instruction is executed, the h fl ag is set to 1 if there is a carry or borrow at bit 11, and cleared to 0 otherwise. when the add.l, sub.l, cmp.l, or neg.l instruction is executed, the h flag is set to 1 if there is a carry or borrow at bit 27, and cleared to 0 otherwise. 4 u undefined r/w user bit can be written to and read from by software using the ldc, stc, andc, orc, and xorc instructions. 3 n undefined r/w negative flag stores the value of the most significant bit of data as a sign bit. 2 z undefined r/w zero flag set to 1 to indicate zero data, and cleared to 0 to indicate non-zero data. 1 v undefined r/w overflow flag set to 1 when an arithmetic overflow occurs, and cleared to 0 otherwise.
rev. 2.00, 03/04, page 25 of 534 bit bit name initial value r/w description 0 c undefined r/w carry flag set to 1 when a carry occurs, and cleared to 0 otherwise. used by: ? add instructions, to indicate a carry ? subtract instructions, to indicate a borrow ? shift and rotate instructi ons, to indicate a carry the carry flag is also used as a bit accumulator by bit manipulation instructions. 2.4.5 initial register values reset exception handling loads the cpu's program co unter (pc) from the vect or table, clears the trace (t) bit in exr to 0, and se ts the interrupt mask (i) bits in ccr and exr to 1. the other ccr bits and the general registers are not initialized. note that the stack pointer (er7) is undefined. the stack pointer should therefore be initialized by an mov.l instruction executed immediately after a reset.
rev. 2.00, 03/04, page 26 of 534 2.5 data formats the h8s/2000 cpu can process 1-bit, 4-bit bcd, 8-bit (byte), 16-bit (word), and 32-bit (longword) data. bit-manipulation instructions operate on 1-bit data by accessing bit n (n = 0, 1, 2, ?, 7) of byte operand data. the daa and das decimal-adjust instructions treat byte data as two digits of 4-bit bcd data. 2.5.1 general register data formats figure 2.9 shows the data formats of general registers. 70 70 msb lsb msb lsb 70 43 don't care don't care don't care 70 43 70 don't care 65432 710 70 don't care 65432 710 don't care rnh rnl rnh rnl rnh rnl data type register number data format byte data byte data 4-bit bcd data 4-bit bcd data 1-bit data 1-bit data upper lower upper lower figure 2.9 general register data formats (1)
rev. 2.00, 03/04, page 27 of 534 15 0 msb lsb 15 0 msb lsb 31 16 msb 15 0 lsb en rn ern : en : rn : rnh : rnl : msb : lsb : general register er general register e general register r general register rh general register rl most significant bit least significant bit data type data format register number word data word data rn en longword data [legend] ern figure 2.9 general register data formats (2)
rev. 2.00, 03/04, page 28 of 534 2.5.2 memory data formats figure 2.10 shows the data formats in memory . the h8s/2000 cpu can access word data and longword data in memory, but word or longword data must begin at an even address. if an attempt is made to access word or longword data at an od d address, no address error occurs but the least significant bit of the address is regarded as 0, so the access starts at the preceding address. this also applies to instruction fetches. when sp (er7) is used as an address register to access the stack, the operand size should be word size or longword size. 70 76 543210 msb lsb msb msb lsb lsb data type address 1-bit data byte data word data address l address l address 2m address 2m+1 longword data address 2n address 2n+1 address 2n+2 address 2n+3 data format figure 2.10 memory data formats
rev. 2.00, 03/04, page 29 of 534 2.6 instruction set the h8s/2000 cpu has 65 types of instructions. th e instructions are classi fied by function as shown in table 2.1. table 2.1 instruction classification function instructions size types mov b/w/l 5 pop * 1 , push * 1 w/l ldm, stm l data transfer movfpe * 3 , movtpe * 3 b add, sub, cmp, neg b/w/l 19 addx, subx, daa, das b inc, dec b/w/l adds, subs l mulxu, divxu, mulxs, divxs b/w extu, exts w/l arithmetic operations tas * 4 b logic operations and, or, xor, not b/w/l 4 shift shal, shar, shll, sh lr, rotl, rotr, rotxl, rotxr b/w/l 8 bit manipulation bset, bclr, bnot, btst, bld, bild, bst, bist, band, biand, bor, bior, bxor, bixor b 14 branch b cc * 2 , jmp, bsr, jsr, rts ? 5 system control trapa, rte, sleep, ldc, stc, andc, orc, xorc, nop ? 9 block data transfer eepmov ? 1 total: 65 notes: b: byte size; w: word size; l: longword size. 1. pop.w rn and push.w rn are ident ical to mov.w @sp+, rn and mov.w rn, @- sp. pop.l ern and push.l ern are identic al to mov.l @sp+, ern and mov.l ern, @-sp. 2. b cc is the general name for conditional branch instructions. 3. cannot be used in this lsi. 4. only register er0, er1, er4, or er5 should be used when using the tas instruction.
rev. 2.00, 03/04, page 30 of 534 2.6.1 table of instructions classified by function tables 2.3 to 2.10 summarize th e instructions in each functional category. the notation used in tables 2.3 to 2.10 is defined below. table 2.2 operation notation symbol description rd general register (destination) * rs general register (source) * rn general register * ern general register (32-bit register) (ead) destination operand (eas) source operand exr extended control register ccr condition-code register n n (negative) flag in ccr z z (zero) flag in ccr v v (overflow) flag in ccr c c (carry) flag in ccr pc program counter sp stack pointer #imm immediate data disp displacement + addition ? subtraction multiplication division logical and logical or logical exclusive or move not (logical complement) :8/:16/:24/:32 8-, 16-, 24-, or 32-bit length note: general registers include 8-bit registers (r0h to r7h, r0l to r7l), 16-bit registers (r0 to r7, e0 to e7), and 32-bit registers (er0 to er7).
rev. 2.00, 03/04, page 31 of 534 table 2.3 data transfer instructions instruction size * function mov b/w/l (eas) rd, rs (ead) moves data between two general registers or between a general register and memory, or moves immediate data to a general register. movfpe b cannot be used in this lsi. movtpe b cannot be used in this lsi. pop w/l @sp+ rn pops a general register from the sta ck. pop.w rn is identical to mov.w @sp+, rn. pop.l ern is iden tical to mov.l @sp+, ern push w/l rn @-sp pushes a general register onto the stack. push.w rn is identical to mov.w rn, @-sp. push.l ern is identical to mov.l ern, @-sp. ldm l @sp+ rn (register list) pops two or more general registers from the stack. stm l rn (register list) @-sp pushes two or more general registers onto the stack. note: size refers to the operand size. b: byte w: word l: longword
rev. 2.00, 03/04, page 32 of 534 table 2.4 arithmetic operations instructions (1) instruction size * function add sub b/w/l rd rs rd, rd #imm rd performs addition or subtraction on da ta in two general registers, or on immediate data and data in a general register. (subtraction on immediate data and data in a general register cannot be performed in bytes. use the subx or add instruction.) addx subx b rd rs c rd, rd #imm c rd performs addition or subtraction with carry on data in two general registers, or on immediate data and data in a general register. inc dec b/w/l rd 1 rd, rd 2 rd adds or subtracts the value 1 or 2 to or from data in a general register. (only the value 1 can be added to or subtracted from byte operands.) adds subs l rd 1 rd, rd 2 rd, rd 4 rd adds or subtracts the value 1, 2, or 4 to or from data in a 32-bit register. daa das b rd (decimal adjust) rd decimal-adjusts an addition or subtracti on result in a general register by referring to ccr to produce 4-bit bcd data. mulxu b/w rd rs rd performs unsigned multiplication on data in two general registers: either 8 bits 8 bits 16 bits or 16 bits 16 bits 32 bits. mulxs b/w rd rs rd performs signed multiplication on data in two general registers: either 8 bits 8 bits 16 bits or 16 bits 16 bits 32 bits. divxu b/w rd rs rd performs unsigned division on data in two general registers: either 16 bits 8 bits 8-bit quotient and 8-bit remainder or 32 bits 16 bits 16-bit quotient and 16-bit remainder. note: size refers to the operand size. b: byte w: word l: longword
rev. 2.00, 03/04, page 33 of 534 table 2.4 arithmetic operations instructions (2) instruction size * 1 function divxs b/w rd rs rd performs signed division on data in two general registers: either 16 bits 8 bits 8-bit quotient and 8-bit remainder or 32 bits 16 bits 16-bit quotient and 16-bit remainder. cmp b/w/l rd ? rs, rd ? #imm compares data in a general register with data in another general register or with immediate data, and sets t he ccr bits according to the result. neg b/w/l 0 ? rd rd takes the two's complement (arith metic complement) of data in a general register. extu w/l rd (zero extension) rd extends the lower 8 bits of a 16-bit register to word size, or the lower 16 bits of a 32-bit register to longword size, by padding with zeros on the left. exts w/l rd (sign extension) rd extends the lower 8 bits of a 16-bit register to word size, or the lower 16 bits of a 32-bit register to longword size, by extending the sign bit. tas * 2 b @erd ? 0, 1 ( of @erd) tests memory contents, and sets the mo st significant bit (bit 7) to 1. notes: 1. size refers to the operand size. b: byte w: word l: longword 2. only register er0, er1, er4, or er5 should be used when using the tas instruction.
rev. 2.00, 03/04, page 34 of 534 table 2.5 logic operations instructions instruction size * function and b/w/l rd rs rd, rd #imm rd performs a logical and operation on a general register and another general register or immediate data. or b/w/l rd rs rd, rd #imm rd performs a logical or operation on a general register and another general register or immediate data. xor b/w/l rd rs rd, rd #imm rd performs a logical exclusive or operation on a general register and another general register or immediate data. not b/w/l rd rd takes the one's complement (logical complement) of data in a general register. note: size refers to the operand size. b: byte w: word l: longword table 2.6 shift instructions instruction size * function shal shar b/w/l rd (shift) rd performs an arithmetic shift on data in a general register. 1-bit or 2 bit shift is possible. shll shlr b/w/l rd (shift) rd performs a logical shift on data in a general register. 1-bit or 2 bit shift is possible. rotl rotr b/w/l rd (rotate) rd rotates data in a general register. 1-bit or 2 bit rotation is possible. rotxl rotxr b/w/l rd (rotate) rd rotates data including the carry flag in a general register. 1-bit or 2 bit rotation is possible. note: size refers to the operand size. b: byte w: word l: longword
rev. 2.00, 03/04, page 35 of 534 table 2.7 bit manipulation instructions (1) instruction size * function bset b 1 ( of ) sets a specified bit in a general register or memory operand to 1. the bit number is specified by 3-bit immediat e data or the lower three bits of a general register. bclr b 0 ( of ) clears a specified bit in a general register or memory operand to 0. the bit number is specified by 3-bit immedi ate data or the lower three bits of a general register. bnot b ( of ) ( of ) inverts a specified bit in a general register or memory operand. the bit number is specified by 3-bit immediat e data or the lower three bits of a general register. btst b ( of ) z tests a specified bit in a general register or memory operand and sets or clears the z flag accordingly. the bit number is specified by 3-bit immediate data or the lower three bits of a general register. band b c ( of ) c logically ands the carry flag with a specified bit in a general register or memory operand and stores the result in the carry flag. biand b c ( of ) c logically ands the carry flag with the inverse of a specified bit in a general register or memory operand and stores the result in the carry flag. the bit number is specif ied by 3-bit immediate data. bor b c ( of ) c logically ors the carry flag with a specified bit in a general register or memory operand and stores the result in the carry flag. bior b c ( of ) c logically ors the carry flag with the inverse of a specified bit in a general register or memory operand and stores the result in the carry flag. the bit number is specif ied by 3-bit immediate data. note: size refers to the operand size. b: byte
rev. 2.00, 03/04, page 36 of 534 table 2.7 bit manipulation instructions (2) instruction size * function bxor b c ( of ) c logically exclusive-ors the carry flag with a specified bit in a general register or memory operand and stores the result in the carry flag. bixor b c ( of ) c logically exclusive-ors the carry flag with the inverse of a specified bit in a general register or memory oper and and stores the result in the carry flag. the bit number is spec ified by 3-bit immediate data. bld b ( of ) c transfers a specified bit in a general register or memory operand to the carry flag. bild b ( of ) c transfers the inverse of a specified bit in a general register or memory operand to the carry flag. the bit number is specified by 3-bit immediate data. bst b c ( of ) transfers the carry flag value to a specified bit in a general register or memory operand. bist b c (. of ) transfers the inverse of the carry flag value to a specified bit in a general register or memory operand. the bit number is specified by 3- bit immediate data. note: size refers to the operand size. b: byte
rev. 2.00, 03/04, page 37 of 534 table 2.8 branch instructions instruction size function bcc ? branches to a specified address if a specified condition is true. the branching conditions are listed below. mnemonic description condition bra (bt) always (true) always brn (bf) never (false) never bhi high c z = 0 bls low or same c z = 1 bcc (bhs) carry clear (high or same) c = 0 bcs (blo) carry set (low) c = 1 bne not equal z = 0 beq equal z = 1 bvc overflow clear v = 0 bvs overflow set v = 1 bpl plus n = 0 bmi minus n = 1 bge greater or equal n v = 0 blt less than n v = 1 bgt greater than z (n v) = 0 ble less or equal z (n v) = 1 jmp ? branches unconditionally to a specified address. bsr ? branches to a subroutine at a specified address jsr ? branches to a subroutine at a specified address rts ? returns from a subroutine
rev. 2.00, 03/04, page 38 of 534 table 2.9 system control instructions instruction size * function trapa ? starts trap-instructi on exception handling. rte ? returns from an exception-handling routine. sleep ? causes a transition to a power-down state. ldc b/w (eas) ccr, (eas) exr moves the memory operand contents or immediate data to ccr or exr. although ccr and exr are 8-bit registers, word-size transfers are performed between them and memory . the upper 8 bits are valid. stc b/w ccr (ead), exr (ead) transfers ccr or exr contents to a general register or memory operand. although ccr and exr are 8-bit registers, word-size transfers are performed between them and memory. the upper 8 bits are valid. andc b ccr #imm ccr, exr #imm exr logically ands the ccr or exr contents with immediate data. orc b ccr #imm ccr, exr #imm exr logically ors the ccr or exr contents with immediate data. xorc b ccr #imm ccr, exr #imm exr logically exclusive-ors the ccr or exr contents with immediate data. nop ? pc + 2 pc only increments the program counter. note: size refers to the operand size. b: byte w: word
rev. 2.00, 03/04, page 39 of 534 table 2.10 block data transfer instructions instruction size function eepmov.b ? if r4l 0 then repeat @er5+ @er6+ r4l?1 r4l until r4l = 0 else next: eepmov.w ? if r4 0 then repeat @er5+ @er6+ r4?1 r4 until r4 = 0 else next: transfers a data block. starting from the address set in er5, transfers data for the number of bytes set in r4l or r4 to the address location set in er6. execution of the next instruction be gins as soon as the transfer is completed. 2.6.2 basic instruction formats the h8s/2000 cpu instructions consist of 2-byte (1-word) units. an instruction consists of an operation field (op), a register field (r), an eff ective address extension (e a), and a condition field (cc). figure 2.11 shows examples of instruction formats. ? ? ? ?
rev. 2.00, 03/04, page 40 of 534 op op rn rm nop, rts, etc. add.b rn, rm, etc. mov.b @(d:16, rn), rm, etc. rn rm op ea (disp) op cc ea (disp) bra d:16, etc. (1) operation field only (2) operation field and register fields (3) operation field, register fields, and effective address extension (4) operation field, effective address extension, and condition field figure 2.11 instruction formats (examples) 2.7 addressing modes and effective address calculation the h8s/2000 cpu supports the eight addressing modes listed in table 2.11. each instruction uses a subset of these ad dressing modes. arithmetic and logic operations instructions can use the register direct and immediate addressing modes. data transfer instructions can use all addressing modes except program-counter relative and memory indirect. bit manipulation instructions can use register direct, register indirect, or absolute addressing mode to specify an operand, and register direct (bset, bclr, bnot, and btst instructions) or immediate (3 -bit) addressing mode to specify a bit number in the operand. table 2.11 addressing modes no. addressing mode symbol 1 register direct rn 2 register indirect @ern 3 register indirect with displa cement @(d:16,ern)/@(d:32,ern) 4 register indirect with post-increment register indirect with pre-decrement @ern+ @?ern 5 absolute address @aa:8/@aa:16/@aa:24/@aa:32 6 immediate #xx: 8/#xx:16/#xx:32 7 program-counter relati ve @(d:8,pc)/@(d:16,pc) 8 memory indirect @@aa:8
rev. 2.00, 03/04, page 41 of 534 2.7.1 register direct ? ? ? ? ? ? ? ? ?
rev. 2.00, 03/04, page 42 of 534 a 24-bit absolute address (@aa:24 ) indicates the address of a pr ogram instruction. the upper 8 bits are all assumed to be 0 (h'00). table 2.12 absolute address access ranges absolute address normal mode advanced mode data address 8 bits (@aa:8) h 'ff00 to h'ffff h'ffff00 to h'ffffff 16 bits (@aa:16) h'0000 to h'ffff h'000000 to h'007fff, h'ff8000 to h'ffffff 32 bits (@aa:32) h'000000 to h'ffffff program instruction address 24 bits (@aa:24) 2.7.6 immediate ? ? ? ??? ? ? ???
rev. 2.00, 03/04, page 43 of 534 in normal mode, the memory operand is a word operand and the branch address is 16 bits long. in advanced mode, the memory operand is a longword operand, the first byte of which is assumed to be 0 (h'00). note that the top area of the addr ess range in which the branch addr ess is stored is also used for the exception vector area. for further detail s, refer to section 4, exception handling. if an odd address is specified in word or longword memory access, or as a branch address, the least significant bit is regarded as 0, causing data to be accessed or the instruction code to be fetched at the address preceding the specified address. (for further information, see section 2.5.2, memory data formats.) specified by @aa:8 specified by @aa:8 branch address branch address reserved (a) normal mode * (b) advanced mode note: for this lsi, normal mode is not available. figure 2.12 branch address specificati on in memory indirect addressing mode
rev. 2.00, 03/04, page 44 of 534 2.7.9 effective address calculation table 2.13 indicates how effec tive addresses are calculated in each addressing mode. in normal mode, the upper 8 bits of the effective address are ignored in order to generate a 16-bit address. table 2.13 effective ad dress calculation (1) no 1 offset 1 2 4 r op 31 0 31 23 2 3 register indirect with displacement @(d:16,ern) or @(d:32,ern) 4 r op disp r op rm op rn 31 0 31 0 r op don't care 31 23 31 0 don't care 31 0 disp 31 0 31 0 31 23 31 0 don't care 31 23 31 0 don't care 24 24 24 24 addressing mode and instruction format effective address calculation effective address (ea) register direct (rn) general register contents general register contents general register contents general register contents sign extension register indirect (@ern) register indirect with post-increment or pre-decrement register indirect with post-increment @ern+ register indirect with pre-decrement @-ern 1, 2, or 4 1, 2, or 4 operand size byte word longword operand is general register contents.
rev. 2.00, 03/04, page 45 of 534 table 2.13 effective ad dress calculation (2) no 5 op 31 23 31 0 don't care abs @aa:8 7 h'ffff op 31 23 31 0 don't care @aa:16 op @aa:24 @aa:32 abs 15 16 31 23 31 0 don't care 31 23 31 0 don't care abs op abs 6 op imm #xx:8/#xx:16/#xx:32 8 24 24 24 24 addressing mode and instruction format absolute address immediate effective address calculation effective address (ea) sign extension operand is immediate data. 31 23 7 program-counter relative @(d:8,pc)/@(d:16,pc) memory indirect @@aa:8 normal mode* advanced mode 31 0 don't care 23 0 disp 0 31 23 31 0 don't care disp op 23 op 8 abs 31 0 abs h'000000 7 8 0 15 31 23 31 0 don't care 15 h'00 16 op abs 31 0 abs h'000000 7 8 0 31 24 24 24 pc contents sign extension memory contents memory contents note: for this lsi, normal mode is not available.
rev. 2.00, 03/04, page 46 of 534 2.8 processing states the h8s/2000 cpu has four main processing stat es: the reset state, exception handling state, program execution state, and prog ram stop state. figure 2.13 indicates the state transitions. ? res input goes low, all current processing stops and the cpu enters the reset state. all interrupts are masked in the reset state. reset exception handli ng starts when the res signal changes from low to high. for details, refer to section 4, exception handling. the reset state can also be entere d by a watchdog timer overflow. ? ? ?
rev. 2.00, 03/04, page 47 of 534 exception handling state software standby mode reset state * 1 sleep mode power-down state * 3 program execution state = high = high, = low reset state hardware standby mode * 2 request for exception handling interrupt request external interrupt request ssby = 0 sleep instruction ssby = 1 sleep instruction end of exception handling notes: 1. from any state except hardware standby mode, a transition to the reset state occurs whenever goes low. a transition can also be made to the reset state when the watchdog timer overflows. 2. in every state, when the stby pin becomes low, the hardware standby mode is entered. 3. for details, refer to section 16, power-down modes. figure 2.13 state transitions 2.9 usage note 2.9.1 note on bit manipulation instructions bit manipulation instructions such as bset, bclr, bnot, bst, and bist read data in byte units, perform bit manipulation, and write data in byte units. thus, care must be taken when these bit manipulation instructions are executed for a register or port including write-only bits. in addition, the bclr instruction can be used to clear the flag of an internal i/o register. in this case, if the flag to be cleared has been set by an interrupt processing routine, the flag need not be read before executing the bclr instruction.
rev. 2.00, 03/04, page 48 of 534
rev. 2.00, 03/04, page 49 of 534 section 3 mcu operating modes 3.1 operating mode selection this lsi supports single operating mode (mode 2). the operating mode is determined by the setting of the mode pins ( md2 and md1). table 3.1 shows the mcu operating mode selection. table 3.1 mcu operating mode selection mcu operating mode md2 md1 cpu operating mode description on-chip rom 2 1 1 advanced mode extended mode with on-chip rom single-chip mode enabled mode 2 is single-chip mode after a reset. the cp u can switch to extended mode by setting bit expe in mdcr to 1. modes 0, 1, 3, 5, and 7 cannot be used in this lsi. modes 4 and 6 are specific modes. thus, mode pins should be set to enable mode 2 in normal program execution state. mode pins should not be changed during operation. mode 4 is a boot mode to program/erase the flash memory. mode 6 is on-chip emulation mode. this mode is controlled by the on-chip emulator (e10a) via the jtag interface, and on-chip emulation can be performed.
rev. 2.00, 03/04, page 50 of 534 3.2 register descriptions the following registers are related to the operating mode. ? ? bit bit name initial value r/w description 7 expe 0 r/w extended mode enable specifies extended mode. 0: single-chip mode 1: extended mode 6 to 3 ? all 0 r reserved these bits are always read as 0 and cannot be modified. 2 1 mds2 mds1 ? * ? * r r mode select 2, 1 these bits indicate the input levels at mode pins ( md2 and md1) (the current operating mode). bits mds2 and mds1 correspond to md2 and md1, respectively. mds2 and mds1 are read-only bits and they cannot be written to. the mode pin ( md2 and md1) input levels are latched into these bits when mdcr is read. these latches are canceled by a reset. 0 ? 0 r reserved this bit is always read as 0 and cannot be modified. note: * the initial values are deter mined by the settings of the md2 and md1 pins.
rev. 2.00, 03/04, page 51 of 534 3.2.2 system control register (syscr) syscr monitors a reset source, selects the interrupt control mo de and the detection edge for nmi, and controls on-chip ram address space. bit bit name initial value r/w description 7, 6 ? all 0 r/w reserved the initial value should not be changed. 5 4 intm1 intm0 0 0 r r/w these bits select the cont rol mode of the interrupt controller. for details on t he interrupt control modes, see section 5.6, interrupt control modes and interrupt operation. 00: interrupt control mode 0 01: interrupt control mode 1 10: setting prohibited 11: setting prohibited 3 xrst 1 r external reset this bit indicates the reset source. a reset is caused by an external reset input, or when the watchdog timer overflows. 0: a reset is caused when the watchdog timer overflows. 1: a reset is caused by an external reset. 2 nmieg 0 r/w nmi edge select selects the valid edge of the nmi interrupt input. 0: an interrupt is requested at the falling edge of nmi input 1: an interrupt is requested at the rising edge of nmi input 1 ? 0 r/w reserved the initial value should not be changed. 0 rame 1 r/w ram enable enables or disables on-chip ram. the rame bit is initialized when the reset state is released. 0: on-chip ram is disabled 1: on-chip ram is enabled
rev. 2.00, 03/04, page 52 of 534 3.3 operating modes 3.3.1 mode 2 the cpu can access a 16-mbyte address space in advanced mode. the on-chip rom is enabled. after a reset, the lsi is set to single-chip mode. to access an exte rnal address space, bit expe in mdcr should be set to 1. in extended mode, ports 6 and 7 function as input ports after a reset. ports 6 and 7 function as an address bus by setting the ahoe, amoe, aloe bits to 1 in the port function control register 1 (pfcr1). ports 5 and 8 function as a data bus, and parts of ports 9 and a function bus control signals. 3.3.2 pin functions table 3.2 shows pin functions in operating mode 2. table 3.2 pin functions in operating mode 2 port mode 2 port 5 i/o port * /data bus i/o port 6 i/o port * /address bus output port 7 i/o port * /address bus output port 8 i/o port * /data bus i/o port 9 p97 i/o port * /clock i/o p96 to p90 input port * /control signal output port a pa3 to pa1 i/o port * /address bus output/control signal output pa0 i/o port * /address bus output [legend] * : after a reset
rev. 2.00, 03/04, page 53 of 534 3.4 address map figure 3.1 shows the address map in each operating mode. rom: 256 kbytes ram: 32 kbytes mode 2 (expe = 1) advanced mode extended mode with on-chip rom mode 2 (expe = 0) advanced mode single chip mode rom: 256 kbytes ram: 32 kbytes h'000000 h'ff7000 h'fff000 h'000000 on-chip rom on-chip rom external address space external address space external address space internal i/o registers internal i/o registers internal i/o registers internal i/o registers on-chip ram/external address space * on-chip ram/reserved area * reserved area reserved area reserved area h'fffc00 h'ffffff note: * these areas can be used as an on-chip ram area by setting the rame bit in syscr to 1. h'fffc00 h'ffff00 h'ffff40 h'ffffff h'ffff00 h'ffff40 h'040000 h'040000 h'ff7000 h'fff000 figure 3.1 address map
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rev. 2.00, 03/04, page 55 of 534 section 4 exception handling 4.1 exception handling types and priority as table 4.1 indicates, exception handling may be caused by a reset, interrupt, or trap instruction. exception handling is prioritized as shown in table 4.1. if two or more exceptions occur simultaneously, they are accepted and processed in order of priority. table 4.1 exception types and priority priority exception type start of exception handling high reset starts immediately after a low-to-high transition of the res pin, or when the watchdog timer overflows. interrupt starts when execution of the current instruction or exception handling ends, if an interrupt request has been issued. interrupt detection is not performed on completion of andc, orc, xorc, or ldc in struction execution, or on completion of reset exception handling. low trap instruction started by execution of a trap (t rapa) instruction. trap instruction exception handling requests are accepted at all times in program execution state.
rev. 2.00, 03/04, page 56 of 534 4.2 exception sources and exception vector table different vector addresses are assigned to differen t exception sources. table 4.2 lists the exception sources and their v ector addresses. table 4.2 exception handling vector table vector address exception source vector number advanced mode reset 0 h'000000 to h'000003 reserved for system use 1 ? 6 h'000004 to h'000007 ? h'000018 to h'00001b external interrupt (nmi) 7 h'00001c to h'00001f 8 h'000020 to h'000023 9 h'000024 to h'000027 10 h'000028 to h'00002b trap instruction (four sources) 11 h'00002c to h'00002f reserved for system use 12 ? 15 h'000030 to h'000033 ? h'00003c to h'00003f irq0 16 h'000040 to h'000043 irq1 17 h'000044 to h'000047 irq2 18 h'000048 to h'00004b irq3 19 h'00004c to h'00004f irq4 20 h'000050 to h'000053 irq5 21 h'000054 to h'000057 irq6 22 h'000058 to h'00005b external interrupt external interrupt external interrupt external interrupt external interrupt external interrupt external interrupt external interrupt irq7 23 h'00005c to h'00005f internal interrupt * 24 ? 110 h'000060 to h'000063 ? h'0001b8 to h'0001bb note: * for details on the internal interrupt vector table, see section 5.5, interrupt exception handling vector table.
rev. 2.00, 03/04, page 57 of 534 4.3 reset a reset has the highest exception priority. when the res pin goes low, all processing halts and this lsi enters the reset. to ensure that this lsi is reset, hold the res pin low for at least 20 ms at power-on. to reset the chip during operation, hold the res pin low for at least 20 states. a reset initializes the internal state of the cpu and the re gisters of on-chip peripheral modules. the chip can also be reset by overflow of the watchdog timer. for details, see section 10, watchdog timer (wdt). 4.3.1 reset exception handling when the res pin goes high after being held low for the necessary time, this lsi starts reset exception handling as follows: 1. the internal state of the cpu and the registers of the on-chip peripheral modules are initialized and the i bit is set to 1 in ccr. 2. the reset exception handling vector address is read and transferred to the pc, and program execution starts from the ad dress indicated by the pc. figure 4.1 shows an example of the reset sequence.
rev. 2.00, 03/04, page 58 of 534 res internal address bus internal read signal internal write signal internal data bus vector fetch (1), (3) (2), (4) (5) (6) reset exception handling vector address ((1) = h'000000, (3) = h'000002) start address (contents of reset exception handling vector address) start address ((5) = (2)(4)) first program instruction (1) (3) (5) high internal processing prefetch of first program instruction (2) (4) (6) figure 4.1 reset sequence 4.3.2 interrupts after reset if an interrupt is accepted after a reset and before the stack pointer (sp) is initialized, the pc and ccr will not be saved correctly, leading to a program crash. to prevent this, all interrupt requests, including nmi, are disabled immediately after a re set. since the first instruction of a program is always executed immediatel y after the reset state ends, make sure that this instruction initializes the stack pointer (example: mov.l #xx: 32, sp). 4.3.3 on-chip peripheral modules after reset is cancelled after a reset is cancelled, the module stop cont rol register (mstpcr) is initialized, and all modules except the dmac operat e in module stop mode. therefore, the registers of on-chip peripheral modules cannot be read from or written to. to read from and write to these registers, clear module stop mode.
rev. 2.00, 03/04, page 59 of 534 4.4 interrupt exception handling interrupts are controlled by the interrupt contro ller. the sources to start interrupt exception handling are external interrupt so urces (nmi and irq7 to irq0) and internal interrupt sources from the on-chip peripheral modules. nmi is an in terrupt with the highest priority. for details, see section 5, interrupt controller. interrupt exception handling is conducted as follows: 1. the values in the program counter (pc) and condition code register (ccr) are saved to the stack. 2. a vector address corresponding to the interrupt source is generated, the start address is loaded from the vector table to the pc, and prog ram execution begins from that address. 4.5 trap instruction exception handling trap instruction exception handling starts when a trapa instruction is executed. trap instruction exception handling can be executed at all times in the program execution state. trap instruction exception handling is conducted as follows: 1. the values in the program counter (pc) and condition code register (ccr) are saved to the stack. 2. a vector address corresponding to the interrupt source is generated, the start address is loaded from the vector table to the pc, and prog ram execution starts from that address. the trapa instruction fetches a start address from a vector table entry corresponding to a vector number from 0 to 3, as specified in the instruction code. table 4.3 shows the status of ccr after execution of trap instruction exception handling. table 4.3 status of ccr after trap instruction exception handling ccr interrupt control mode i ui 0 set to 1 retains value prior to execution 1 set to 1 set to 1
rev. 2.00, 03/04, page 60 of 534 4.6 stack status after exception handling figure 4.2 shows the stack after completion of trap instruction exception handling and interrupt exception handling. ccr pc (24 bits) sp figure 4.2 stack status after exception handling 4.7 usage note when accessing word data or longword data, this lsi assumes that the lowest address bit is 0. the stack should always be accessed in words or longwo rds, and the value of the stack pointer (sp: er7) should always be kept even. use the following instructions to save registers: push.w rn (or mov.w rn, @-sp ) push.l ern (or mov.l ern, @-sp ) use the following instructions to restore registers: pop.w rn (or mov.w @sp+, rn ) pop.l ern (or mov.l @sp+, ern ) setting sp to an odd value may lead to a malfunction. figure 4.3 shows an operation example when the sp value is odd.
rev. 2.00, 03/04, page 61 of 534 ccr : pc : r1l : sp : condition code register program counter general register r1l stack pointer trapa instruction executed sp set to h'fffeff data saved above sp mov.b r1l, @-er7 executed contents of ccr lost address legend note: this diagram illustrates an example in which the interrupt control mode is 0. h'fffefa h'fffefb h'fffefc h'fffefd h'fffeff sp ccr sp sp r1l pc pc figure 4.3 operation when sp value is odd
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rev. 2.00, 03/04, page 63 of 534 section 5 interrupt controller 5.1 features ? two interrupt control modes any of two interrupt control modes can be set by means of the intm1 and intm0 bits in the system control register (syscr). ? priorities settable with icr an interrupt control register (icr) is provided for setting interrupt priorities. three priority levels can be set for each module for all interrupts except nmi. ? independent vector addresses all interrupt sources are assigned independent vector addresses, making it unnecessary for the source to be identified in the interrupt handling routine. ? nine external interrupts nmi is the highest-priority interrupt, and is accep ted at all times. rising edge or falling edge detection can be selected for nmi. falling-edge, rising-edge, or both-edge detection, or level sensing, can be selected for irq7 to irq0 . syscr nmi input irq input internal interrupt sources wovi0 to usbi2 nmieg intm1, intm0 nmi input irq input isr iscr ier icr interrupt controller priority level determination interrupt request vector number i, ui ccr cpu icr : iscr : ier : isr : syscr : interrupt control register irq sense control register irq enable register irq status register system control register [legend] figure 5.1 block diagra m of interrupt controller
rev. 2.00, 03/04, page 64 of 534 5.2 input/output pins table 5.1 summarizes the pins of the interrupt controller. table 5.1 pin configuration symbol i/o function nmi input nonmaskable external interrupt rising edge or falling edge can be selected irq7 to irq0 input maskable external interrupts rising edge, falling edge, or both edges, or level sensing, can be selected individually for each pin. whether the irqn interrupt is input from the irqn or ( irqn ) is selectable. (n = 7 to 0) 5.3 register descriptions the interrupt controller has the following registers. for details on the system control register (syscr), see section 3.2.2, system control register (syscr), and for details on the irq sense port select register (issr), see section 8.11 .2, irq sense port select register (issr). ? interrupt control registers a to c (icra to icrc) ? address break control register (abrkcr) ? break address registers a to c (pbara to pbarc) ? irq sense control registers h, l (iscrh, iscrl) ? irq enable register (ier) ? irq status register (isr) 5.3.1 interrupt control regist ers a to c (icra to icrc) the icr registers set interrupt control levels for interrupts other than nmi. the correspondence between interrupt sources and icra to icrc settings is shown in table 5.2. bit bit name initial value r/w description 7 to 0 icrn7 to ircn0 all 0 r/w interrupt control level 0: corresponding interrupt source is interrupt control level 0 (no priority) 1: corresponding interrupt source is interrupt control level 1 (priority) note: n: a to c
rev. 2.00, 03/04, page 65 of 534 table 5.2 correspondence between interrupt source and icr register bit bit name icra icrb icrc 7 icrn7 irq0 ? sci 6 icrn6 irq1 suspend recover interrupt ? 5 icrn5 irq2, irq3 dmac ? 4 icrn4 irq4, irq5 ? ? 3 icrn3 irq6, irq7 tmr_0 ? 2 icrn2 ? tmr_1 ? 1 icrn1 wdt ? ? 0 icrn0 refresh timer ? usb2 note: n: a to c ? : reserved. the write value should always be 0. 5.3.2 address break control register (abrkcr) abrkcr controls the address break s. when both the cmf flag an d bie flag are set to 1, an address break is requested. bit bit name initial value r/w description 7 cmif undefined r/w condition match flag address break source flag. indicates that an address specified by bara to barc is prefetched. [clearing condition] when an exception handling is executed for an address break interrupt. [setting condition] when an address specified by bara to barc is prefetched while the bie flag is set to 1. 6 to 1 ? all 0 r reserved these bits are always read as 0 and cannot be modified. 0 bie 0 r/w break interrupt enable enables or disables address break. 0: disabled 1: enabled
rev. 2.00, 03/04, page 66 of 534 5.3.3 break address registers a to c (pbara to pbarc) the pbar registers specify an addr ess that is to be a break addres s. an address in which the first byte of an instruction exists shou ld be set as a break address. ? pbara bit bit name initial value r/w description 7 to 0 a23 to a16 all 0 r/w addresses 23 to 16 the a23 to a16 bits are compared with a23 to a16 in the internal address bus. ? pbarb bit bit name initial value r/w description 7 to 0 a15 to a8 all 0 r/w addresses 15 to 8 the a15 to a8 bits are compared with a15 to a8 in the internal address bus. ? pbarc bit bit name initial value r/w description 7 to 1 a7 to a1 all 0 r/w addresses 7 to 1 the a7 to a1 bits are compared with a7 to a1 in the internal address bus. 0 ? 0 r reserved this bit is always read as 0 and cannot be modified.
rev. 2.00, 03/04, page 67 of 534 5.3.4 irq sense control registers h, l (iscrh, iscrl) the iscr registers select the source that generates an interrupt request at pins irq7 to irq0 . the irq7 to irq0 pins can be switched to input pins by setting the irq sense port select register (issr). ? iscrh bit bit name initial value r/w description 7 6 irq7scb irq7sca 0 0 r/w r/w 5 4 irq6scb irq6sca 0 0 r/w r/w 3 2 irq5scb irq5sca 0 0 r/w r/w 1 0 irq4scb irq4sca 0 0 r/w r/w irqn sense control b irqn sense control a 00: interrupt request generated at low level of irqn input 01: interrupt request generated at falling edge of irqn input 10: interrupt request generated at rising edge of irqn input 11: interrupt request generated at both falling and rising edges of irqn input (n = 7 to 4) ? iscrl bit bit name initial value r/w description 7 6 irq3scb irq3sca 0 0 r/w r/w 5 4 irq2scb irq2sca 0 0 r/w r/w 3 2 irq1scb irq1sca 0 0 r/w r/w 1 0 irq0scb irq0sca 0 0 r/w r/w irqn sense control b irqn sense control a 00: interrupt request generated at low level of irqn input 01: interrupt request generated at falling edge of irqn input 10: interrupt request generated at rising edge of irqn input 11: interrupt request generated at both falling and rising edges of irqn input (n = 3 to 0)
rev. 2.00, 03/04, page 68 of 534 5.3.5 irq enable register (ier) ier controls the enabling and disabling of interrupt requests irq7 to irq0. bit bit name initial value r/w description 7 6 5 4 3 2 1 0 irq7e irq6e irq5e irq4e irq3e irq2e irq1e irq0e 0 0 0 0 0 0 0 0 r/w r/w r/w r/w r/w r/w r/w r/w irqn enable (n = 7 to 0) the irqn interrupt request is enabled when this bit is 1. 5.3.6 irq status register (isr) isr is a flag register that indicates the st atus of irq7 to irq0 interrupt requests. bit bit name initial value r/w description 7 6 5 4 3 2 1 0 irq7f irq6f irq5f irq4f irq3f irq2f irq1f irq0f 0 0 0 0 0 0 0 0 r/w r/w r/w r/w r/w r/w r/w r/w [setting condition] when the interrupt source selected by the iscr registers occurs [clearing conditions] ? when reading irqnf flag when irqnf = 1, then writing 0 to irqnf flag ? when interrupt exception handling is executed when low-level detection is set and irqn input is high ? when irqn interrupt exception handling is executed when falling-edge, rising-edge, or both-edge detection is set (n = 7 to 0)
rev. 2.00, 03/04, page 69 of 534 5.4 interrupt sources 5.4.1 external interrupts there are two external interrupts: nmi and irq7 to irq0. these interrupts can be used to restore this lsi from software standby mode. nmi interrupt: nmi is the highest-priority interrupt , and is always accepted by the cpu regardless of the interrupt control mode or the status of the cpu interrupt mask bits. the nmieg bit in syscr can be used to select whether an interrupt is requested at a rising edge or a falling edge on the nmi pin. irq7 to irq0 interrupts: interrupts irq7 to irq0 are reques ted by an input signal at pins irq7 to irq0 . interrupts irq7 to irq0 have the following features: ? the interrupt exception handling for interrupt requests irq7 to irq0 can be started at an independent vector address. ? using iscr, it is possible to select whether an interrupt is generated by a low level, falling edge, rising edge, or both edges, at pins irq7 to irq0. ? enabling or disabling of interrupt requests irq7 to irq0 can be selected with ier. ? the status of interrupt requests irq7 to irq0 is indicated in isr. isr flags can be cleared to 0 by software. the detection of irq7 to irq0 interrupts does not depend on whether the relevant pin has been set for input or output. however, when a pin is used as an external interrupt input pin, do not clear the corresponding port ddr to 0 to use the pin as an i/o pin for another function. a block diagram of interrupts irq7 to irq0 is shown in figure 5.2. irqn interrupt request irqne irqnf s r q clear signal edge/level detection circuit irqnsca, irqnscb input n = 7 to 0 figure 5.2 block diagram of interrupts irq7 to irq0
rev. 2.00, 03/04, page 70 of 534 5.4.2 internal interrupts internal interrupts issued from the on-chip peripheral modules have the following features: ? for each on-chip peripheral module there are fl ags that indicate the in terrupt request status, and enable bits that individual ly select enabling or disabling of these interrupts. when the enable bit for a particular interrupt source is set to 1, an interrupt request is sent to the interrupt controller. ? the control level for each inte rrupt can be set by icr. 5.5 interrupt exception handling vector table table 5.3 lists interrupt exception handling sources, vector addresses, and interrupt priorities. for default priorities, the lower the vector number, th e higher the priority. modules set at the same priority will conform to their default priori ties. priorities within a module are fixed. an interrupt control level can be specified for a m odule to which an icr bit is assigned. interrupt requests from modules that are set to interrupt co ntrol level 1 (priority) by the icr bit setting and the i and ui bits in ccr are given priority and pr ocessed before interrupt requests from modules that are set to interrupt control level 0 (no priority). table 5.3 interrupt sources, vector a ddresses, and interrupt priorities origin of interrupt source name vector number vector address icr priority external pin nmi 7 h'00001c ? high irq0 16 h'000040 icra7 irq1 17 h'000044 icra6 irq2 irq3 18 19 h'000048 h'00004c icra5 irq4 irq5 20 21 h'000050 h'000054 icra4 irq6 irq7 22 23 h'000058 h'00005c icra3 ? reserved for system use 24 h'000060 ? wdt wovi0 (interval timer) 25 h'000064 icra1 refresh timer cmi (compare match) 26 h'000068 icra0 ? address break 27 h'00006c ? ? reserved for system use 28 29 h'000070 h'000074 ? low
rev. 2.00, 03/04, page 71 of 534 origin of interrupt source name vector number vector address icr priority external pin susri (suspend recover interrupt) 30 h'000078 icrb6 high ? reserved for system use 31 to 33 h'00007c to h'000084 ? dmac dend0 dend1 dend2 dend3 34 35 36 37 h'000088 h'00008c h'000090 h'000094 icrb5 ? reserved for system use 38 to 63 h'000098 to h'0000fc ? tmr_0 cmia0 (compare match a) cmib0 (compare match b) ovi0 (overflow) reserved for system use 64 65 66 67 h'000100 h'000104 h'000108 h'00010c icrb3 tmr_1 cmia1 (compare match a) cmib1 (compare match b) ovi1 (overflow) reserved for system use 68 69 70 71 h'000110 h'000114 h'000118 h'00011c icrb2 ? reserved for system use 72 to 79 h'000120 to h'00013c ? sci eri0 (reception error 0) rxi0 (reception completion 0) txi0 (transmission data empty 0) tei0 (transmission end 0) 80 81 82 83 h'000140 h'000144 h'000148 h'00014c icrc7 ? reserved for system use 84 to 107 h'000150 to h'0001ac ? usb2 usbi1 usbi0 usbi2 reserved for system use 108 109 110 111 h'0001b0 h'0001b4 h'0001b8 h'0001bc icrc0 low
rev. 2.00, 03/04, page 72 of 534 5.6 interrupt control modes and interrupt operation the interrupt controller has two modes: interrupt control mode 0 and interrupt control mode 1. interrupt operations differ depending on the interrupt control mode. nmi interrupts and address break interrupts are always accepted except for in reset state or in hardware standby mode. the interrupt control mode is selected by syscr. table 5.4 shows the interrupt control modes. table 5.4 interrupt control modes syscr interrupt control mode intm1 intm0 priority setting registers interrupt mask bits description 0 0 0 icr i interrupt mask control is performed by the i bit. priority levels can be set with icr. 1 1 icr i, ui 3-level interrupt mask control is performed by the i bit. priority levels can be set with icr. figure 5.3 shows a block diagram of the priority decision circuit. icr ui i default priority determination vector number interrupt acceptance control and 3-level mask control interrupt source interrupt control modes 0 and 1 figure 5.3 block diagram of interrupt cont rol operation
rev. 2.00, 03/04, page 73 of 534 interrupt acceptance contro l and 3-level control: in interrupt control modes 0 and 1, interrupt acceptance control and 3-leve l mask control is performed by means of the i and ui bits in ccr and icr (control level). table 5.5 shows the interrupts that can be accepted in each interrupt control mode. table 5.5 interrupts acceptable in each interrupt control mode interrupt control mode i bit ui bit nm i, address break peripheral module interrupt 0 0 ? o o (all interrupts) * 1 ? o x 1 0 ? o o (all interrupts) * 1 0 o o (interrupts with icr = 1) 1 o x [legend] ? : don't care note: * interrupt control level 1 has priority. default priority determination: the priority is determined for the selected interrupt, and a vector number is generated. if the same value is set for icr, acceptance of mu ltiple interrupts is enab led, and so only the interrupt source with the highest priority according to the preset default priorities is selected and has a vector number generated. interrupt sources with a lower priority than the accepted interrupt source are held pending. table 5.6 shows operations and control signal functions in each interrupt control mode. table 5.6 operations and control signal f unctions in each interrupt control mode interrupt setting interrupt acceptance control 3-level control default priority control mode intm1 intm0 i ui icr determination t (trace) 0 0 0 o im ? pr o ? 1 1 o im im pr o ? [legend] o: interrupt operation control performed im: used as an interrupt mask bit pr: sets priority ? : not used
rev. 2.00, 03/04, page 74 of 534 5.6.1 interrupt control mode 0 in interrupt control mode 0, interrupt requests other than nmi and address break are masked by icr and the i bit of the ccr in the cpu. the interr upt requests are held pending when the i bit is set to 1. figure 5.4 shows a flowchar t of the interrupt acceptance operation. 1. if an interrupt source occurs when the corresponding interrupt enable bit is set to 1, an interrupt request is sent to the interrupt controller. 2. according to the interrupt control level specif ied in icr, the interrupt controller only accepts an interrupt request with interrupt control level 1 (priority), and holds pending an interrupt request with interrupt control level 0 (no priority ). if several interrupt requests are issued, an interrupt request with the high est priority is accepted according to the priority order, an interrupt handling is requested to the cpu, and other interrupt requests are held pending. 3. if the i bit in ccr is set to 1, only nmi an d address break interrup ts are accepted by the interrupt controller, and other interrupt requests are held pending. if the i bit is cleared to 0, any interrupt request is accepted. 4. when the cpu accepts an interrupt request, it starts interrupt ex ception handling after execution of the current instruction has been completed. 5. the pc and ccr are saved to the stack area by interrupt exception handling. the pc saved on the stack shows the address of the first instruction to be executed after returning from the interrupt handling routine. 6. next, the i bit in ccr is set to 1. this masks all interrupts except for nmi and address break interrupts. 7. the cpu generates a vector address for the accepted interrupt and starts execution of the interrupt handling routine at the address indicated by the contents of the vector address in the vector table.
rev. 2.00, 03/04, page 75 of 534 program execution state interrupt generated? nmi an interrupt with interrupt control level 1? irq0 irq1 usbi2 irq0 irq1 usbi2 i = 0 save pc and ccr i 1 read vector address branch to interrupt handling routine yes no yes yes yes no no yes no yes no yes yes no no yes yes no hold pending figure 5.4 flowchart of pro cedure up to interrupt acceptan ce in interrupt control mode 0
rev. 2.00, 03/04, page 76 of 534 5.6.2 interrupt control mode 1 in interrupt control mode 1, mask control is app lied to three levels for irq and on-chip peripheral module interrupt requests by comparing the i and ui bits in ccr in the cpu, and the icr setting. the interrupt requests are held pending when the i bit is set to 1. 1. an interrupt request with inte rrupt control level 0 is accepted when the i bit in ccr is cleared to 0. when the i bit is set to 1, the interrupt request is held pending. 2. an interrupt request with interr upt control level 1 is accepted when the i bit or ui bit in ccr is cleared to 0. when both i and ui bits are set to 1, the interrupt request is held pending. for instance, the state transition when the interrupt enable bit corresponding to each interrupt is set to 1, and icra to icrc are set to h'20, h'00, and h'00, respectively (irq2 and irq3 interrupts are set to interrupt control level 1, and other interr upts are set to interrupt control level 0) is shown below. figure 5.5 shows a state transition diagram. 1. all interrupt requests are accepted when i = 0. (priority order: nmi > irq2 > irq3 > irq0 > irq1 > address break ?) 2. only nmi, irq2, irq3, and address break inte rrupt requests are accepted when i = 1 and ui = 0. 3. only nmi and address break interrupt requ ests are accepted when i = 1 and ui = 1. only nmi and address break interrupt requests are accepted all interrupt requests are accepted exception handling execution or i 1, ui 1 i 0 i 1, ui 0 i 0 ui 0 exception handling execution or ui 1 only nmi, address break, and interrupt control level 1 interrupt requests are accepted figure 5.5 state tr ansition in interru pt control mode 1
rev. 2.00, 03/04, page 77 of 534 figure 5.6 shows a flowchart of the interrupt acceptance operation. 1. if an interrupt source occurs when the corresponding interrupt enable bit is set to 1, an interrupt request is sent to the interrupt controller. 2. according to the interrupt control level specif ied in icr, the interrupt controller only accepts an interrupt request with interrupt control level 1 (priority), and holds pending an interrupt request with interrupt control level 0 (no priority ). if several interrupt requests are issued, an interrupt request with the highest priority is accepted according to th e priority order, an interrupt handling is requested to the cpu, and other interrupt requests are held pending. 3. an interrupt request with interr upt control level 1 is accepted when the i bit is cleared to 0, or when the i bit is set to 1 while the ui bit is cleared to 0. an interrupt request with interrupt control level 0 is accepted when the i bit is cleared to 0. when the i bit is set to 1, only an nmi or address break interr upt request is accepted, and other interrupts are held pending. when both the i and ui bits are set to 1, only an nmi or address break interrupt request is accepted, and other interr upts are held pending. when the i bit is cleared to 0, the ui bit is not affected. 4. when the cpu accepts an interrupt request, it starts interrupt ex ception handling after execution of the current instru ction has been completed. 5. the pc and ccr are saved to the stack area by interrupt exception handling. the pc saved on the stack shows the address of the first instruction to be executed after returning from the interrupt handling routine. 6. the i and ui bits in ccr are set to 1. this masks all interrupts except for an nmi or address break interrupt. 7. the cpu generates a vector address for the accepted interrupt and starts execution of the interrupt handling routine at the address indicated by the contents of the vector address in the vector table.
rev. 2.00, 03/04, page 78 of 534 program excution state interrupt generated? nmi an interrupt with interrupt control level 1? irq0 irq1 usbi2 irq0 irq1 usbi2 ui = 0 save pc and ccr i 1, ui 1 read vector address branch to interrupt handling routine yes no yes yes yes no no yes no yes no yes yes no no yes yes no hold pending i = 0 i = 0 yes yes no no figure 5.6 flowchart of procedure up to interrupt acceptance in interrupt control mode 1 5.6.3 interrupt exception handling sequence figure 5.7 shows the interrupt exception handlin g sequence. the example shown is for the case where interrupt control mode 0 is set in advan ced mode, and the program area and stack area are in on-chip memory.
rev. 2.00, 03/04, page 79 of 534 (14) (12) (10) (6) (4) (2) (1) (5) (7) (9) (11) (13) prefetch of instruction in interrupt-handling routine vector fetch stack access instruction prefetch internal processing internal processing interrupt is accepted interrupt level decision and wait for end of instruction interrupt request signal internal address bus internal read signal internal write signal internal data bus (3) (1) (2) (4) (3) (5) (7) instruction prefetch address (instruction is not executed. address is saved as pc contents, becoming return address.) instruction code (not executed) instruction prefetch address (instruction is not executed.) sp ? 2 sp ? 4 saved pc and ccr vector address starting address of interrupt-handling routine (contents of vector address) starting address of interrupt-handling routine ((13) = (10) (12)) first instruction in interrupt-handling routine (6) (8) (9) (11) (10) (12) (13) (14) (8) figure 5.7 interrupt exception handling
rev. 2.00, 03/04, page 80 of 534 5.6.4 interrupt response times table 5.7 shows interrupt response times ? the intervals between generation of an interrupt request and execution of the first instruction in the interrupt handling routine. the execution status symbols used in table 5.7 are explained in table 5.8. table 5.7 interrupt response times no. execution status advanced mode 1 interrupt priority determination * 1 3 2 number of wait st ates until executing instruction ends * 2 1 to (19 + 2s i ) 3 pc, ccr stack save 2s k 4 vector fetch 2s i 5 instruction fetch * 3 2s i 6 internal processing * 4 2 total (using on-chip memory) 12 to 32 notes: 1. two states in case of intern al interrupt. 2. refers to mulxs and divxs instructions. 3. prefetch after interrupt acceptance a nd prefetch of interrupt handling routine. 4. internal processing after interrupt acceptan ce and internal processing after vector fetch. table 5.8 number of states in interr upt handling routine execution status object of access external device 8-bit bus 16-bit bus symbol internal memory 2-state access 3-state access 2-state access 3-state access instruction fetch s i 1 4 6 + 2m 2 3 + m branch address read s j stack manipulation s k [legend] m: number of wait states in external device access.
rev. 2.00, 03/04, page 81 of 534 5.7 usage notes 5.7.1 conflict between interrupt generation and disabling when an interrupt enable bit is cleared to 0 to disable interrupt requests, the disabling becomes effective after execution of the inst ruction. when an interrupt enable bit is cleared to 0 by an instruction such as bclr or mov, and if an in terrupt is generated during execution of the instruction, the interrupt concerned will still be enabled on completion of the instruction, so interrupt exception handling for that interrupt will be executed on completion of the instruction. however, if there is an interrupt request of high er priority than that interrupt, interrupt exception handling will be executed for the higher-priority in terrupt, and the lower-priority interrupt will be ignored. the same rule is also applied when an interrupt source flag is cleared to 0. figure 5.8 shows an example in which the cmiea bit in the tmr's tcr register is cleared to 0. the above conflict will not occur if an enable bit or interrupt source flag is cleared to 0 while the interrupt is masked. internal address bus internal write signal cmiea cmfa cmia interrupt signal tcr write cycle by cpu cmia exception handling tcr address figure 5.8 conflict between int errupt generation and disabling
rev. 2.00, 03/04, page 82 of 534 5.7.2 instructions th at disable interrupts the instructions that disable interrupts are ldc, andc, orc, and xorc. after any of these instructions are executed, all interrupts includin g nmi are disabled and the next instruction is always executed. when the i bit or ui bit is set by one of these instructions, the new value becomes valid two states after ex ecution of the instruction ends. 5.7.3 interrupts during execu tion of eepmov instruction interrupt operation differs between the eepmov.b instruction and the eepmov.w instruction. with the eepmov.b instruction, an interrupt request (including nmi) issued during the transfer is not accepted until the move is completed. with the eepmov.w instruction, if an interrupt request is issued during the transfer, interrupt exception handling starts at a break in the transfer cycle. the pc value saved on the stack in this case is the address of the next inst ruction. therefore, if an interrupt is generated during execution of an eepmov.w instruction, the following coding should be used. l1: eepmov.w mov.w r4,r4 bne l1
rev. 2.00, 03/04, page 83 of 534 section 6 bus controller (bsc) this lsi has an on-chip bus controller (bsc) that manages the external address space divided into four areas. the bus specifications such as the bu s width and number of access states can be set independently for each area. therefore multiple memories and external i/o devices can be connected easily to each area. the bus controller also has a bus arbitration function, and controls the operation of the bus masters ? the cpu and dma controller (dmac). a block diagram of the bus controller is shown in figure 6.1. 6.1 features ? manages external address space in area units manages the external address space divided into four areas of 2/10 mbytes bus specifications can be se t independently for each area dram interface can be set ? basic bus interface chip select signals ( cs0 to cs3 ) can be output for areas 0 to 3 8-bit access or 16-bit access can be selected for each area 2-state access or 3-state access can be selected for each area program wait states can be inserted for each area cs assertion period extend states can be inserted for each area ? dram interface dram interface can be set for area 2 multiplex output of row/column address (8/9/10/11 bits) byte and word control by cas2 method burst operation can be performed in high-speed page mode tp cycle insertion to ensure ras precharge time cas before ras refresh (cbr refresh) or self refresh can be selected ? idle cycle insertion idle cycles can be inserted when external re ad cycles between different areas are continued idle cycles can be inserted when write cycles are continued after a read cycle idle cycles can be inserted when accesse s between different areas are continued ? write buffer function an external write cycle and internal access can be executed in parallel dmac single address mode and internal access can be executed in parallel
rev. 2.00, 03/04, page 84 of 534 ? bus arbitration function includes a bus arbiter that arbitrates bu s mastership between the cpu and dmac ? others a refresh counter (refresh timer) can be used as an interval timer area decoder cs3 to cs 0 internal bus control signals internal data bus control registers internal address bus external bus controller internal bus arbiter internal bus controller cpu bus request signal dmac bus request signal cpu bus acknowledge signal dmac bus acknowledge signal dramcr [legend] acscr : csacr : wtcr : bcr : rdncr : dramcr : draccr : refcr : rtcnt : rtcor : access control register cs assertion period control register wait control register bus control register read strobe timing control register dram control register dram access control register refresh control register refresh timer counter refresh time constant register refcr draccr rtcnt rtcor acscr wtcr csacr bcr rdncr figure 6.1 block diagram of bus controller
rev. 2.00, 03/04, page 85 of 534 6.2 input/output pins table 6.1 shows the pin configuration of the bus controller. table 6.1 pin configuration name symbol i/o function address strobe as output strobe signal indicating that normal space is accessed and address output on address bus is enabled. read rd output strobe signal indicating that normal space is being read. high write hwr output strobe signal indicating that normal space is written to, and upper half (d15 to d8) of data bus is enabled. low write lwr output strobe signal indicating that normal space is written to, and lower half (d7 to d0) of data bus is enabled. chip select 0 cs0 output strobe signal indicating that area 0 is selected. chip select 1 cs1 output strobe signal indicating that area 1 is selected chip select 2/ row address strobe cs2 / ras output strobe signal indicating that area 2 is selected/dram row address strobe signal chip select 3 cs3 output strobe signal indicating that area 3 is selected. upper column address strobe ucas output 16-bit dram space upper column address strobe signal or 8-bit dram space column address strobe signal lower column address strobe lcas output 16-bit dram space lower column address strobe signal data transfer acknowledge 3 (dmac) dack3 output data transfer acknowledge signal for single address transfer by dmac channel 3. data transfer acknowledge 2 (dmac) dack2 output data transfer acknowledge signal for single address transfer by dmac channel 2. data transfer acknowledge 1 (dmac) dack1 output data transfer acknowledge signal for single address transfer by dmac channel 1. data transfer acknowledge 0 (dmac) dack0 output data transfer acknowledge signal for single address transfer by dmac channel 0.
rev. 2.00, 03/04, page 86 of 534 6.3 register descriptions the bus controller has the following registers. ? access control register (acscr) ? cs assertion period control register (csacr) ? wait control register (wtcr) ? bus control register (bcr) ? read strobe timing control register (rdncr) ? dram control register (dramcr) ? dram access control register (draccr) ? refresh control register (refcr) ? refresh timer counter (rtcnt) ? refresh time constant register (rtcor)
rev. 2.00, 03/04, page 87 of 534 6.3.1 access contro l register (acscr) acscr designates each area in the external addres s space as either 8-bi t access space or 16-bit access space. acscr designates each area in the exte rnal address space as either 2-state access space or 3-state access space. acscr is initialized to h'ff at a reset or in hardware standby mode but not initialized in software standby mode. bit bit name initial value r/w description 7 6 5 4 abw3 abw2 abw1 abw0 1 1 1 1 r/w r/w r/w r/w area 3 to 0 bus width control these bits select whether the corresponding area is to be designated as 8-bit access space or 16-bit access space. 0: area n is designated as 16-bit access space 1: area n is designated as 8-bit access space 3 2 1 0 ast3 ast2 ast1 ast0 1 1 1 1 r/w r/w r/w r/w area 3 to 0 access state control these bits select whether the corresponding area is to be designated as 2-state access space or 3-state access space. wait state insertion is enabled or disabled at the same time. 0: area n is designated as 2-state access space wait state insertion in area n access is disabled 1: area n is designated as 3-state access space wait state insertion in area n access is enabled (n = 3 to 0)
rev. 2.00, 03/04, page 88 of 534 6.3.2 cs assertion period co ntrol register (csacr) csacr selects whether or not the assertion period of the basic bus interface chip select signals ( csn ) and address signals is to be extended. extending the assertion period of the csn and address signals allows flexible interfacing to external i/o devices. bit bit name initial value r/w description 7 6 5 4 csxh3 csxh2 csxh1 csxh0 0 0 0 0 r/w r/w r/w r/w cs and address signal assertion period control 1 these bits specify whether or not the t h cycle is to be inserted (see figure 6.2). when an area for which the csxhn bit is set to 1 is accessed, a one-state t h cycle, in which only the csn and address signals are asserted, is inserted befor e the normal access cycle. 0: in area n basic bus interface access, the csn and address assertion period (t h ) is not extended 1: in area n basic bus interface access, the csn and address assertion period (t h ) is extended 3 2 1 0 csxt3 csxt2 csxt1 csxt0 0 0 0 0 r/w r/w r/w r/w cs and address signal assertion period control 2 these bits specify whether or not the t t cycle is to be inserted (see figure 6.2). when an area for which the csxtn bit is set to 1 is accessed, a one-state t t cycle, in which only the csn and address signals are asserted, is inserted befor e the normal access cycle. 0: in area n basic bus interface access, the csn and address assertion period (t t ) is not extended 1: in area n basic bus interface access, the csn and address assertion period (t t ) is extended (n = 3 to 0)
rev. 2.00, 03/04, page 89 of 534 t h t 1 t 2 t 3 t t , note: n = 3 to 0 read (when rdnn = 0) data bus data bus address bus cycle read data write data write figure 6.2 cs and address assertio n period extension (example of 3-state a ccess space and rdnn = 0)
rev. 2.00, 03/04, page 90 of 534 6.3.3 wait control register (wtcr) wtcr selects the number of prog ram wait states for each area in the external address space. bit bit name initial value r/w description 15 ? 0 r reserved this bit is always read as 0 and cannot be modified. 14 13 12 w32 w31 w30 1 1 1 r/w r/w r/w area 3 wait control 2 to 0 these bits select the number of program wait states when accessing area 3 while ast3 bit in acscr = 1. 000: program wait not inserted 001: 1 program wait state inserted 010: 2 program wait states inserted 011: 3 program wait states inserted 100: 4 program wait states inserted 101: 5 program wait states inserted 110: 6 program wait states inserted 111: 7 program wait states inserted 11 ? 0 r reserved this bit is always read as 0 and cannot be modified. 10 9 8 w22 w21 w20 1 1 1 r/w r/w r/w area 2 wait control 2 to 0 these bits select the number of program wait states when accessing area 2 while ast2 bit in acscr = 1. 000: program wait not inserted 001: 1 program wait state inserted 010: 2 program wait states inserted 011: 3 program wait states inserted 100: 4 program wait states inserted 101: 5 program wait states inserted 110: 6 program wait states inserted 111: 7 program wait states inserted 7 ? 0 r reserved this bit is always read as 0 and cannot be modified.
rev. 2.00, 03/04, page 91 of 534 bit bit name initial value r/w description 6 5 4 w12 w11 w10 1 1 1 r/w r/w r/w area 1 wait control 2 to 0 these bits select the number of program wait states when accessing area 1 while ast1 bit in acscr = 1. 000: program wait not inserted 001: 1 program wait state inserted 010: 2 program wait states inserted 011: 3 program wait states inserted 100: 4 program wait states inserted 101: 5 program wait states inserted 110: 6 program wait states inserted 111: 7 program wait states inserted 3 ? 0 r reserved this bit is always read as 0 and cannot be modified. 2 1 0 w02 w01 w00 1 1 1 r/w r/w r/w area 0 wait control 2 to 0 these bits select the number of program wait states when accessing area 0 while ast0 bit in acscr = 1. 000: program wait not inserted 001: 1 program wait state inserted 010: 2 program wait states inserted 011: 3 program wait states inserted 100: 4 program wait states inserted 101: 5 program wait states inserted 110: 6 program wait states inserted 111: 7 program wait states inserted
rev. 2.00, 03/04, page 92 of 534 6.3.4 bus control register (bcr) bcr is used for idle cycle settings and enabling or disabling of the write data buffer function. bit bit name initial value r/w description 15 to 9 ? all 0 r/w reserved these bits can be read from or written to. however, the write value should always be 0. 8 wdbe 0 r/w write data buffer enable the write data buffer function can be used for an external write cycle or dmac single address transfer cycle. 0: write data buffer function not used 1: write data buffer function used 7 to 4 ? all 0 r/w reserved these bits can be read from or written to. however, the write value should always be 0. 3 2 idle1 idle0 0 0 r/w r/w idle cycle enable these bits enable the idle cycle insertion. 00: idle cycle insertion is disabled. 01: when read accesses to different areas are continued or external accesses are continued after a single address transfer, idle cycle insertion is enabled. 10: when read accesses to different areas are continued, external accesses are continued after a single address transfer, or write accesses are continued after a read, idle cycle insertion is enabled. 11: when read accesses to different areas are continued, external accesses are continued after a single address transfer, write accesses are continued after a read, or read accesses are continued after a write, idle cycle insertion is enabled. 1 0 idlc1 idlc0 0 0 r/w r/w idle cycle state number select these bits specify the number of idle cycle states to be inserted. 00: 1 state 01: 2 states 10: 3 states 11: 4 states
rev. 2.00, 03/04, page 93 of 534 6.3.5 read strobe timing control register (rdncr) rdncr selects the read strobe signal ( rd ) negation timing in a read access to normal space. bit bit name initial value r/w description 7 6 5 4 rdn3 rdn2 rdn1 rdn0 0 0 0 0 r/w r/w r/w r/w read strobe timing control 3 to 0 these bits set the negation ti ming of the read strobe in a corresponding area read access. as shown in figure 6.3, the read strobe for an area for which the rdnn bit is set to 1 is negated one half-state earlier than that for an area for which the rdnn bit is cleared to 0. the read data setup and hold time specifications are also one half-state earlier. 0: in an area n read access, the rd is negated at the end of the read cycle 1: in an area n read access, the rd is negated one half-state before the end of the read cycle (n = 3 to 0) 3 to 0 ? all 0 r/w reserved these bits can be read from or written to. however, the write value should always be 0. bus cycle t 1 t 2 data data rdnn = 0 rdnn = 1 legend n = 3 to 0 t 3 figure 6.3 read strobe negation timing (example of 3-state access space)
rev. 2.00, 03/04, page 94 of 534 6.3.6 dram control register (dramcr) dramcr is used to make dram interface settings. bit bit name initial value r/w description 15 ? 0 r/w reserved this bit can be read from or written to. however, the write value should always be 0. 14 rast 0 r/w ras assertion timing select selects whether, in dram access, the ras signal is asserted from the start of the t r cycle (rising edge of ) or from the falling edge of . figure 6.4 shows the relationship between the rast bit setting and the ras assertion timing. 0: ras is asserted from falling edge in t r cycle 1: ras is asserted from start of t r cycle 13 ? 0 r/w reserved this bit can be read from or written to. however, the write value should always be 0. 12 cast 0 r/w column address output cycle number select selects whether the column address output cycle in dram access comprises 3 states or 2 states. 0: column address output cycle comprises 2 states 1: column address output cycle comprises 3 states 11 to 9 ? all 0 r/w reserved these bits can be read from or written to. however, the write value should always be 0. 8 dset 0 r/w dram space setting specifies area 2 as dram space. 0: area 2 is specified as normal space 1: area 2 is specifies as dram space 7 be 0 r/w burst access enable selects enabling or disabling of burst access to areas designated as dram space. dram space burst access is performed in fast page mode. when using edo page mode dram, the rd signal must be connected as the oe signal. 0: full access 1: access in fast page mode
rev. 2.00, 03/04, page 95 of 534 bit bit name initial value r/w description 6 rcdm 0 r/w ras down mode when access to dram space is interrupted by an access to normal space, an access to an internal i/o register, etc., this bit selects whether the ras signal is held low while waiting for the next dram access ( ras down mode), or is driven high again ( ras up mode). the setting of this bit is valid only when the be bit is set to 1. if this bit is cleared to 0 when set to 1 in the ras down state, the ras down state is cleared at that point, and ras goes high. when using dram interface in ras down mode and ras down state is not continu ed, a 1-state idle cycle is inserted to drive ras signal high. 0: ras up mode selected for dram space access 1: ras down mode selected for dram space access 5 dds 0 r/w dmac single address transfer option selects whether full access is always performed or burst access is enabled when dmac single address transfer is performed on the dram interface. when the be bit is cleared to 0 in dramcr, disabling dram burst access, dmac single address transfer is performed in full access mode regardless of the setting of this bit. this bit has no effect on other bus master external accesses or dmac dual address transfers. if this bit is set to 1, the dack output timing is changed. 0: full access is always executed 1: burst access is enabled 4, 3 ? all 0 r/w reserved these bits can be read from or written to. however, the write value should always be 0.
rev. 2.00, 03/04, page 96 of 534 bit bit name initial value r/w description 2 1 0 mxc2 mxc1 mxc0 0 0 0 r/w r/w r/w address multiplex select these bits select the size of the shift toward the lower half of the row address in row address/column address multiplexing. in burst operat ion on the dram interface, these bits also select the row address bits to be used for comparison. 000: 8-bit shift ? when 8-bit access space is designated: row address bits a23 to a8 used for comparison ? when 16-bit access space is designated: row address bits a23 to a9 used for comparison 001: 9-bit shift ? when 8-bit access space is designated: row address bits a23 to a9 used for comparison ? when 16-bit access space is designated: row address bits a23 to a10 used for comparison 010: 10-bit shift ? when 8-bit access space is designated: row address bits a23 to a10 used for comparison ? when 16-bit access space is designated: row address bits a23 to a11 used for comparison 011: 11-bit shift ? when 8-bit access space is designated: row address bits a23 to a11 used for comparison when 16-bit access space is designated: row address bits a23 to a12 used for comparison
rev. 2.00, 03/04, page 97 of 534 t p address rast = 0 ras rast = 1 ras t r t c1 t c2 ucas , lcas bus cycle row address column address figure 6.4 ras signal assertion timing (2-state column address ou tput cycle, full access) 6.3.7 dram access cont rol register (draccr) draccr is used to set the dram interface bus specifications. bit bit name initial value r/w description 7, 6 ? all 0 r/w reserved these bits can be read from or written to. however, the write value should always be 0. 5 4 tpc1 tpc0 0 0 r/w r/w precharge state control these bits select the number of states in the ras precharge cycle in normal access and refreshing. 00: 1 state 01: 2 states 10: 3 states 11: 4 states 3, 2 ? all 0 r/w reserved these bits can be read from or written to. however, the write value should always be 0.
rev. 2.00, 03/04, page 98 of 534 bit bit name initial value r/w description 1 0 rcd1 rcd0 0 0 r/w r/w ras-cas wait control these bits select a wait cycle to be inserted between the ras assert cycle and cas assert cycle. 00: wait cycle not inserted 01: 1-state wait cycle inserted 10: 2-state wait cycle inserted 11: 3-state wait cycle inserted 6.3.8 refresh control register (refcr) refcr specifies dram interface refresh control. bit bit name initial value r/w description 15 cmf 0 r/(w) * compare match flag status flag that indicates a match between the values of rtcnt and rtcor. [clearing conditions] ? when 0 is written to cmf after reading cmf = 1 while the rfshe bit is cleared to 0 ? when cbr refreshing is executed while the rfshe bit is set to 1 [setting condition] when rtcor = rtcnt 14 cmie 0 r/w compare match interrupt enable enables or disables interrupt requests (cmi) by the cmf flag when the cmf flag is set to 1. this bit is valid when refresh control is not performed (rfshe = 0). when the refresh control is performed (rfshe = 1), this bit is always cleared to 0 and cannot be modified. 0: interrupt request by cmf flag disabled 1: interrupt request by cmf flag enabled
rev. 2.00, 03/04, page 99 of 534 bit bit name initial value r/w description 13 12 rcw1 rcw0 0 0 r/w r/w cas - ras wait control these bits select the num ber of wait cycles to be inserted between the cas assert cycle and ras assert cycle in a dram refresh cycle. 00: wait state not inserted 01: 1 wait state inserted 10: 2 wait states inserted 11: 3 wait states inserted 11 ? 0 r/w reserved this bit can be read from or written to. however, the write value should always be 0. 10 9 8 rtck2 rtck1 rtck0 0 0 0 r/w r/w r/w refresh counter clock select these bits select the clock to be used to increment the refresh counter. when the input clock is selected with bits rtck2 to rtck0, the refresh counter begins counting up. 000: count operation halted 001: count on /2 010: count on /8 011: count on /32 100: count on /128 101: count on /512 110: count on /2048 111: count on /4096 7 rfshe 0 r/w refresh control refresh control can be performed. when refresh control is not performed, the refresh timer can be used as an interval timer. 0: refresh control is not performed 1: refresh control is performed 6 ? 0 r/w reserved this bit can be read from or written to. however, the write value should always be 0.
rev. 2.00, 03/04, page 100 of 534 bit bit name initial value r/w description 5 4 rlw1 rlw0 0 0 r/w r/w refresh cycle wait control these bits select the number of wait states to be inserted in a dram interface cas-before-ras refresh cycle. 00: no wait state inserted 01: 1 wait state inserted 10: 2 wait states inserted 11: 3 wait states inserted 3 slfrf 0 r/w self-refresh enable if this bit is set to 1, dram self-refresh mode is selected when a transition is made to the software standby state. this bit is valid when the rfshe bit is set to 1, enabling refresh operations. 0: self-refreshing is disabled 1: self-refreshing is enabled 2 1 0 tpcs2 tpcs1 tpcs0 0 0 0 r/w r/w r/w self-refresh precharge cycle control these bits select the number of states in the precharge cycle immediately after self-refreshing. the number of states in the precharge cycle immediately after self-refreshing are added to the number of states set by bits tpc1 and tpc0 in draccr. 000: [tpc set value] states 001: [tpc set value + 1] states 010: [tpc set value + 2] states 011: [tpc set value + 3] states 100: [tpc set value + 4] states 101: [tpc set value + 5] states 110: [tpc set value + 6] states 111: [tpc set value + 7] states note: only 0 can be written, to clear the flag.
rev. 2.00, 03/04, page 101 of 534 6.3.9 refresh time r counter (rtcnt) rtcnt is an 8-bit readable/writable up-count er. rtcnt counts up using the internal clock selected by bits rtck2 to rtck0 in refcr. when rtcnt matches rtcor (compare match), the cmf flag in refcr is set to 1 and rtcnt is cleared to h'00. if the rfshe bit in ref cr is set to 1 at this time, a refresh cycle is started. if the rfshe bit is cleared to 0 and the cmie bit in refcr is set to 1, a compare match interrupt (cmi) is generated. rtcnt is initialized to h'00 by a reset and in hardware standby mode. it is not initialized in software standby mode. 6.3.10 refresh time constant register (rtcor) rtcor is an 8-bit readable/writable register that sets the period for compare match operations with rtcnt. the values of rtcor and rtcnt ar e constantly compared, and if they match, the cmf flag in refcr is set to 1 and rtcnt is cleared to h'00. rtcor is initialized to h'ff by a reset and in hardware standby mode. it is not initialized in software standby mode.
rev. 2.00, 03/04, page 102 of 534 6.4 bus control 6.4.1 area division the bus controller divides the 16-mbyte address space into areas shown in figure 6.5, and performs bus control for external address space in area units. chip select signals ( cs0 to cs3 ) can be output for each area. area 0 (2 mbytes) h'000000 h'ffffff h'200000 area 1 (2 mbytes) h'400000 area 2 (10 mbytes) h'e00000 area 3 (2 mbytes) figure 6.5 area divisions
rev. 2.00, 03/04, page 103 of 534 6.4.2 address map figure 6.6 shows the address format. a31 to a24 a23 to a21 a23 don't care do not affect the operation. cs space decoded and output cs0 to cs3 signals. reserved does not output a signal. output address signals are output from address pins. 000 cs0 001 cs1 010 cs2 011 100 101 110 111 cs3 a22 a21 a19 to a0 a20 output cs figure 6.6 address format
rev. 2.00, 03/04, page 104 of 534 bits a31 to a24 do not affect the operation. bits a23 to a21 are decoded by the chip select signals (cs3 to cs0) for each area and output. bit a20 is not output externally. bits a19 to a0 are output externally. enabling or disabling external output of bits a19 to a0 can be selected by the setting of pfcr1. for details, refer to section 8.11.1, port function control register 1 (pfcr1). table 6.2 and figure 6.7 show the address map. table 6.2 address map address space type memory type size bus width h'000000 to h'1fffff cs0 space/ on-chip rom space external space/ on-chip rom 2 mbytes 8/16 h'200000 to h'3fffff cs1 space external space 2 mbytes 8/16 h'400000 to h'dfffff cs2 space/ dram space external space/ dram 10 mbytes 8/16 h'e00000 to h'ffffff cs3 space/ on-chip ram space * / i/o space external space/ on-chip ram * /i/o space 2 mbytes 8/16 note: * on-chip ram space when the rame bit in syscr is 1.
rev. 2.00, 03/04, page 105 of 534 h'000000 h'040000 h'ffffff h'fffc00 h'200000 h'400000 h'e00000 h'ff7000 h'fff000 i/o on-chip ram on-chip rom area 0 area 1 area 2 area 3 figure 6.7 address map 6.4.3 bus specifications the external address space bus sp ecifications consist of five el ements: bus width, number of access states, number of program wait states , read strobe timing, and chip select ( cs ) assertion period extension states. the bus width and nu mber of access states fo r on-chip memory and internal i/o registers are fixed, and ar e not affected by the bus controller. bus width: a bus width of 8 or 16 bits can be selected with acscr. an area for which an 8-bit bus is selected functions as an 8-bit access space, and an area for which a 16-bit bus is selected functions as a 16-bit access space.
rev. 2.00, 03/04, page 106 of 534 number of access states: two or three access states can be selected with acscr. an area for which 2-state access is selected functions as a 2-state access space, and an area for which 3-state access is selected functions as a 3-state access space. with the dr am interface, the number of access states may be determined withou t regard to the setting of acscr. when 2-state access space is designated, wait inse rtion is disabled. when 3-state access space is designated, it is possible to insert program waits by means of wtcr. number of program wait states: when 3-state access space is designated by acscr, the number of program wait states to be inserted au tomatically is selected with wtcr. from 0 to 7 program wait states can be selected. table 6.3 shows the bus specifications (bus width, and number of access states and program wait states) for each basic bus interface area. table 6.3 bus specifications for ea ch area (basic bus interface) acscr wtcr bus specificati ons (basic bus interface) abwn astn wn2 wn1 wn0 bus width access states program wait states 0 0 ? ? ? 16 2 0 1 0 0 0 3 0 1 1 1 0 2 1 3 1 0 0 4 1 5 1 0 6 1 7 1 0 ? ? ? 8 2 0 1 0 0 0 3 0 1 1 1 0 2 1 3 1 0 0 4 1 5 1 0 6 1 7 legend n = 3 to 0
rev. 2.00, 03/04, page 107 of 534 read strobe timing: rdncr can be used to select either of two negation timings (at the end of the read cycle or one half-state before the en d of the read cycle) for the read strobe ( rd ) used in the basic bus interface space. chip select ( cs ) assertion period extension states: some external i/o devices require a setup time and hold time between address and cs signals and strobe signals such as rd , hwr , and lwr . csacr can be used to insert states in which only the cs , as , and address signals are asserted before and after a basic bus space access cycle. 6.4.4 memory interfaces the memory interfaces in this lsi comprise a basi c bus interface that allows direct connection of rom, sram, and so on; and a dram interface th at allows direct co nnection of dram. the interface can be selected independently for each area. an area for which the basic bus interface is de signated functions as normal space and an area for which the dram interface is designated functions as dram space the initial state of each area is basic bus interface, 3-state access space. the initial bus width is 8 bits. area 0: area 0 includes on-chip rom and the space excluding on-chip rom is external address space by setting the expe bit in mdcr to 1. when area 0 external space is accessed, the cs0 signal can be output. only basic bus interface can be used for area 0. area 1: all of area 1 is external ad dress space by setting the expe bit in mdcr to 1. when area 1 external address space is accessed, the cs1 signal can be output. only basic bus interface can be used for area 1. area 2: all of area 2 is external ad dress space by setting the expe bit in mdcr to 1. when area 2 external space is accessed, signal cs2 can be output. basic bus interface or dram interface can be sel ected for area 2. with the dram interface, the cs2 signal is used as the ras signal. if area 2 is designated as dram space, large-capac ity (e.g. 64-mbit) dram can be connected. in this case, the cs2 signal is used as the ras signal for dram space.
rev. 2.00, 03/04, page 108 of 534 area 3: area 3 includes the on-chip ram and internal i/o register s. the space excluding the on- chip ram and internal i/o registers is external address space by setting the expe bit in mdcr to 1. the on-chip ram is enabled when the rame bit is set to 1 in the system control register (syscr); when the rame bit is cleared to 0, the on-chip ram is disabled and the corresponding addresses are in exte rnal address space. when area 3 external address space is accessed, the cs3 signal can be output. only the basic bus interface can be us ed for the area 3 memory interface. 6.4.5 chip select signals this lsi can output chip select signals ( cs3 to cs0 ) for areas 3 to 0. the signal outputs low when the corresponding external space area is acc essed. figure 6.8 shows an example of cs3 to cs0 signals output timing. the cs0 pin is placed in the output state by se tting the expe bit in mdcr to 1. pins cs3 to cs1 are placed in the input state after a reset and so the corresponding cs output should be enabled by setting the pfcr1 register when outputting signals cs3 to cs1 . for details, refer to section 8.11.1, port function control register 1 (pfcr1). when area 2 is designated as dram space, output cs2 is used as the ras signal. bus cycle t 1 t 2 t 3 area n external address address bus figure 6.8 csn signal output timing (n = 3 to 0)
rev. 2.00, 03/04, page 109 of 534 6.5 basic bus interface the basic bus interface enables direct connection of rom, sram, and so on. 6.5.1 data size and data alignment data sizes for the cpu and other internal bus masters are byte, word, and longword. the bus controller has a data alignment function, and wh en accessing external address space, controls whether the upper data bus (d15 to d8) or lower data bus (d7 to d0) is used according to the bus specifications for the area being accessed (8-bit access space or 16-b it access space) and the data size. 8-bit access space: figure 6.9 illustrates data alignment co ntrol for the 8-bit access space. with the 8-bit access space, the upper data bus (d15 to d8) is always us ed for accesses. the amount of data that can be accessed at one time is one byte: a word access is performed as two byte accesses, and a longword access, as four byte accesses. d15 d8 d7 d0 upper data bus lower data bus byte size word size 1st bus cycle 2nd bus cycle longword size 1st bus cycle 2nd bus cycle 3rd bus cycle 4th bus cycle figure 6.9 access sizes and data alignment control (8-bit access space) 16-bit access space: figure 6.10 illustrates data alignmen t control for the 16-bit access space. with the 16-bit access space, the upper data bus (d 15 to d8) and lower data bus (d7 to d0) are used for accesses. the amount of data that can be accessed at one time is one byte or one word, and a longword access is exec uted as two word accesses. in byte access, whether the upper or lower data bus is used is determined by whether the address is even or odd. the upper data bus is used for an even address, and the lower data bus for an odd address.
rev. 2.00, 03/04, page 110 of 534 d15 d8 d7 d0 upper data bus lower data bus byte size word size 1st bus cycle 2nd bus cycle longword size even address byte size odd address figure 6.10 access sizes and data al ignment control (16- bit access space) 6.5.2 valid strobes table 6.4 shows the data buses used and valid strobes for the access spaces. in a read, the rd signal is valid for both the upper and the lower half of the data bus. in a write, the hwr signal is valid for the upper half of the data bus, and the lwr signal for the lower half. table 6.4 data buses used and valid strobes area access size read/ write address valid strobe upper data bus (d15 to d8) lower data bus (d7 to d0) byte read ? rd valid invalid 8-bit access space write ? hwr hi-z byte read even rd valid invalid 16-bit access space odd invalid valid write even hwr valid hi-z odd lwr hi-z valid word read ? rd valid valid write ? hwr , lwr valid valid note: hi-z: high-impedance state invalid: input state; input value is ignored. 6.5.3 basic timing 8-bit, 2-state access space: figure 6.11 shows the bus timing for an 8-bit, 2-state access space. when an 8-bit access space is accessed, the upper ha lf (d15 to d8) of the data bus is used.
rev. 2.00, 03/04, page 111 of 534 when all areas are design ated as 8-bit space, the lwr pin can be used as the i/o port. however, when all areas are design ated as 16-bit space, the lwr pin is always fixed high. wait states cannot be inserted. bus cycle t 1 t 2 address bus d15 to d8 valid d7 to d0 invalid read d15 to d8 valid d7 to d0 high impedance write high notes: 1. n = 3 to 0 2. when rdnn = 0 figure 6.11 bus timing fo r 8-bit, 2-state access space
rev. 2.00, 03/04, page 112 of 534 8-bit, 3-state access space: figure 6.12 shows the bus timing for an 8-bit, 3-state access space. when an 8-bit access space is accessed, the upper ha lf (d15 to d8) of the data bus is used. when all areas are design ated as 8-bit space, the lwr pin can be used as the i/o port. however, when all areas are designat ed as 16-bit space, the lwr pin is always fixed high. wait states can be inserted. bus cycle t 1 t 2 address bus d15 to d8 valid d7 to d0 invalid read d15 to d8 valid d7 to d0 write high t 3 high impedance notes: 1. n = 3 to 0 2. when rdnn = 0 figure 6.12 bus timing fo r 8-bit, 3-state access space
rev. 2.00, 03/04, page 113 of 534 16-bit, 2-state access space: figures 6.13 to 6.15 show bus timings for a 16-bit, 2-state access space. when a 16-bit access space is accessed, the upper half (d15 to d8) of the data bus is used for even addresses, and the lower half (d7 to d0) for odd addresses. wait states cannot be inserted. bus cycle t 1 t 2 address bus d15 to d8 valid d7 to d0 invalid read d15 to d8 valid d7 to d0 write high high impedance notes: 1. n = 3 to 0 2. when rdnn = 0 figure 6.13 bus timing for 16-bit, 2-st ate access space (even address byte access)
rev. 2.00, 03/04, page 114 of 534 bus cycle t 1 t 2 address bus d15 to d8 invalid d7 to d0 valid read d15 to d8 d7 to d0 valid write high high impedance notes: 1. n = 3 to 0 2. when rdnn = 0 figure 6.14 bus timing for 16-bit, 2-st ate access space (odd ad dress byte access)
rev. 2.00, 03/04, page 115 of 534 bus cycle t 1 t 2 address bus d15 to d8 valid d7 to d0 valid read d15 to d8 valid d7 to d0 valid write notes: 1. n = 3 to 0 2. when rdnn = 0 figure 6.15 bus timing for 16-bit , 2-state access space (word access)
rev. 2.00, 03/04, page 116 of 534 16-bit, 3-state access space: figures 6.16 to 6.18 show bus timings for a 16-bit, 3-state access space. when a 16-bit access space is accessed, the uppe r half (d15 to d8) of the data bus is used for the even address, and the lower half (d7 to d0) for the odd address. wait states can be inserted. bus cycle t 1 t 2 address bus d15 to d8 valid d7 to d0 invalid read d15 to d8 valid d7 to d0 write high t 3 high impedance notes: 1. n = 3 to 0 2. when rdnn = 0 figure 6.16 bus timing for 16-bit, 3-st ate access space (even address byte access)
rev. 2.00, 03/04, page 117 of 534 bus cycle t 1 t 2 address bus d15 to d8 invalid d7 to d0 valid read d15 to d8 d7 to d0 valid write high t 3 high impedance notes: 1. n = 3 to 0 2. when rdnn = 0 figure 6.17 bus timing for 16-bit, 3-st ate access space (odd ad dress byte access)
rev. 2.00, 03/04, page 118 of 534 bus cycle t 1 t 2 address bus d15 to d8 valid d7 to d0 valid read d15 to d8 valid d7 to d0 valid write t 3 notes: 1. n = 3 to 0 2. when rdnn = 0 figure 6.18 bus timing for 16-bit , 3-state access space (word access)
rev. 2.00, 03/04, page 119 of 534 6.5.4 wait control when accessing external space, th is lsi can extend th e bus cycle by insert ing one or more wait states (t w ). from 0 to 7 wait states can be in serted automatically between the t 2 state and t 3 state on an individual area basis in 3-state access sp ace, according to the setting of wtcr. figure 6.19 shows an example of wait state insertion timing. the settings after a reset are: 3-state acces s and insertion of 7 program wait states. t 1 , data bus notes: 1. n = 3 to 0 2. when rdnn = 0 data bus address bus read write t 2 tw tw tw t 3 read data write data figure 6.19 example of wait state insertion timing
rev. 2.00, 03/04, page 120 of 534 6.5.5 read strobe ( rd ) timing the read strobe ( rd ) timing can be changed for individual areas by setting bits rdn3 to rdn0 to 1 in rdncr. when the dmac is used in single address mode, note that if the rd timing is changed by setting rdnn to 1, the rd timing will change relative to the rise of dack . figure 6.20 shows an example of the timing when the read strobe timing is changed in basic bus 3- state access space. bus cycle t 1 t 2 address bus t 3 data bus data bus rdnn = 0 rdnn = 1 note: n = 3 to 0 figure 6.20 example of read strobe timing
rev. 2.00, 03/04, page 121 of 534 6.5.6 extension of chip select ( cs ) assertion period some external i/o devices require a setu p time and hold time between address and cs signals and strobe signals such as rd , hwr , and lwr . settings can be made in th e csacr register to insert states in which only the cs , as , and address signals are asserted before and after a basic bus space access cycle. extension of the cs assertion period can be set for individual areas. with the cs assertion extension period in write access, the data setup and hold times are less stringent since the write data is output to the data bus. figure 6.21 shows an example of the timing when the cs assertion period is extended in basic bus 3-state access space. t h address bus t 1 t 2 t 3 t t bus cycle data bus , write note: n = 3 to 0 data bus read (when rdnn = 0) read data write data figure 6.21 example of timing when ch ip select assertion period is extended both extension state t h inserted before the basic bus cycle and extension state t t inserted after the basic bus cycle, or only one of these, can be specified for in dividual areas. insertion or non- insertion can be specified for the t h state with the upper 4 bits (csxh3 to csxh0) in the csacr register, and for the t t state with the lower 4 bits (csxt3 to csxt0).
rev. 2.00, 03/04, page 122 of 534 6.6 dram interface in this lsi, external space area 2 can be designated as dram space, and dram interfacing performed. the dram interface al lows dram to be directly co nnected to this lsi. a dram space of 10 mbytes can be se t by means of bit dset in dr amcr. burst operation is also possible, using fast page mode. 6.6.1 setting dram space area 2 is designated as dram space by setting bit dset in dramcr to 1. in dram space, the ras signal is valid. the bus specificati ons for dram space such as the bus width, number of wait states, and so on are de termined according to the settings for area 2. 6.6.2 address multiplexing with dram space, the row address and column ad dress are multiplexed. in address multiplexing, the size of the shift of the row address is select ed with bits mxc2 to mxc0 in dramcr. table 6.5 shows the relation between the settings of bits mxc2 to mxc0 and the shift size. table 6.5 relation between settings of bits mxc2 to mxc0 and address multiplexing dramcr address pins mxc2 mxc1 mxc0 shift size a19 to a16 a15 a14 a13 a12 a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 row address 0 0 0 8 bits a19 to a16 a23 a22 a21 a20 a19 a18 a17 a16 a15 a14 a13 a12 a11 a10 a9 a8 1 9 bits a19 to a16 a15 a23 a22 a21 a20 a19 a18 a17 a16 a15 a14 a13 a12 a11 a10 a9 1 0 10 bits a19 to a16 a15 a14 a23 a22 a21 a20 a19 a18 a17 a16 a15 a14 a13 a12 a11 a10 1 11 bits a19 to a16 a15 a14 a13 a23 a22 a21 a20 a19 a18 a17 a16 a15 a14 a13 a12 a11 1 ? ? reserved (setting prohibited) ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? column address ? ? ? ? a19 to a16 a15 a14 a13 a12 a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0
rev. 2.00, 03/04, page 123 of 534 6.6.3 data bus if the abw2 bit in acscr is set to 1, that area is designated as 8-bit dram space; if the bit is cleared to 0, the area is designated as 16-bit dram space. in 16-bit dram space, 16-bit configuration dram can be connected directly. in 8-bit dram space the upper half of the data bus, d15 to d8, is enabled, while in 16-bit dram space both the upper and lower halves of the data bus, d15 to d0, are enabled. access sizes and data alignment are the same as fo r the basic bus interface: see section 6.5.1, data size and data alignment. 6.6.4 pins used for dram interface table 6.6 shows the pins used for dram interfacing and their functions. although the cs2 pin is in the input state after a reset, the ras signal is output after the dset bit in dramcr is set and dram space is designated. for details, refer to section 8, i/o ports. table 6.6 dram interface pins pin with dram setting name i/o function hwr we write enable output write enable for dram space access cs2 ras row address strobe output row address strobe when area 2 is designated as dram space ucas ucas upper column address strobe output upper column address strobe for 16-bit dram space access or column address strobe for 8- bit dram space access lcas lcas lower column address strobe output lower column address strobe signal for 16-bit dram space access rd oe output enable output output enable signal for dram space access a15 to a0 a15 to a0 address pins output row address/column address multiplexed output d15 to d0 d15 to d0 data pi ns i/o data input/output pins
rev. 2.00, 03/04, page 124 of 534 6.6.5 basic timing figure 6.22 shows the basic access timing for dram space. the four states of the basic timing consist of one t p (precharge cycle) state, one t r (row address output cycle) state, and two t c1 and t c2 (column address output cycle) states. t p ( ) read write , ( ) ( ) data bus ( ) ( ) data bus address bus t r t c1 t c2 row address high high column address figure 6.22 dram basic access timing (rast = 0, cast = 0) when dram space is accessed, the rd signal is output as the oe signal for dram. when connecting dram provided with an edo page mode, the oe signal should be connected to the ( oe ) pin of the dram.
rev. 2.00, 03/04, page 125 of 534 6.6.6 column address output cycle control the column address output cycle can be changed from 2 states to 3 states by setting the cast bit to 1 in dramcr. use the setting that gives the optimum specification values ( cas pulse width, etc.) according to the dram connected and the op erating frequency of this lsi. figure 6.23 shows an example of the timing when a 3-stat e column address output cycle is selected. t p ( ) read write , ( ) ( ) data bus ( ) ( ) data bus address bus t r t c1 t c2 t c3 row address column address high high figure 6.23 example of access timing wi th 3-state column a ddress output cycle (rast = 0)
rev. 2.00, 03/04, page 126 of 534 6.6.7 row address output state control if the rast bit is set to 1 in dramcr, the ras signal goes low from the beginning of the t r state, and the row address hold time and dram read access time are changed relative to the fall of the ras signal. use the optimum setting according to the dram connected and the operating frequency of this lsi. figure 6.24 shows an example of the timing when the ras signal goes low from the beginning of the t r state. t p ( ) read write , ( ) ( ) data bus ( ) ( ) data bus address bus t r t c1 t c2 row address column address high high figure 6.24 example of access timing when ras signal goes low from beginning of t r state (cast = 0) if a row address hold time or read access time is necessary, making a setting in bits rcd1 and rcd0 in draccr allows from one to three t rw states, in which row address output is maintained, to be inserted between the t r cycle, in which the ras signal goes low, and the t c1 cycle, in which the column address is output. use the setting that gives the optimum row address signal hold time relative to the falling edge of the ras signal according to the dram connected and the operating frequency of this lsi. figure 6.25 shows an example of the timing when one t rw state is set.
rev. 2.00, 03/04, page 127 of 534 t p ( ) read write , ( ) ( ) data bus ( ) ( ) data bus address bus t r t rw t c1 t c2 row address column address high high figure 6.25 example of timing with one row address output hold state (rast = 0, cast = 0)
rev. 2.00, 03/04, page 128 of 534 6.6.8 precharge state control when dram is accessed, a ras precharge time must be secu red. with this lsi, one t p state is always inserted when dram space is accessed. from one to four t p states can be selected by setting bits tpc1 and tpc0 in draccr. set the optimum number of t p cycles according to the dram connected and the operating frequency of this lsi. figure 6.26 shows the timing when two t p states are inserted. the setting of bits tpc1 and tpc0 is also valid for t p states in refresh cycles. t p1 ( ) read write , ( ) ( ) data bus ( ) ( ) data bus address bus t p2 t r t c1 t c2 row address column address high high figure 6.26 example of timi ng with two-state precharge cycle (rast = 0, cast = 0)
rev. 2.00, 03/04, page 129 of 534 6.6.9 wait control when inserting wait states in a dram access cy cle, program wait insertion is specified. wait states are inserted to extend the cas assertion period in a read access to dram space, and to extend the write data setup time relative to the falling edge of cas in a write access. when the ast2 bit in acscr is set to 1, from 0 to 7 wait states can be inserted automatically between the t c1 state and t c2 state, according to the settings of wtcr. figures 6.27 and 6.28 show examples of wait cy cle insertion timing in the case of 2-state and 3- state column addres s output cycles. t p address bus t r t c1 t w t w t c2 read write , , ( ) ( ) data bus ( ) ( ) data bus row address column address high high figure 6.27 example of wait state insertion timing (2-state column address output)
rev. 2.00, 03/04, page 130 of 534 t p address bus t r t c1 t w t w t c2 t c3 read write , , ( ) ( ) data bus ( ) ( ) data bus row address column address high high figure 6.28 example of wait state insertion timing (3-state column address output)
rev. 2.00, 03/04, page 131 of 534 6.6.10 byte access control when dram with a 16-bit configuration is c onnected, the 2-cas access me thod is used for the control signals needed for byte access. figure 6.29 shows the cont rol timing for 2-cas access, and figure 6.30 shows an example of 2-cas dram connection. t p ( ) ( ) ( ) d15 to d8 d7 to d0 address bus t r t c1 t c2 row address column address high high figure 6.29 2-cas co ntrol timing (write a ccess to even address: rast = 0, cast = 0)
rev. 2.00, 03/04, page 132 of 534 this lsi (address shift size set to 11 bits) ras ( cs2 ) 2-cas type 128-mbit dram 8-mbyte 16-bit configuration 11-bit column address ras ucas ucas lcas lcas we we rd ( oe ) oe a9 a8 a10 a9 a11 a10 a12 a11 a8 a7 a7 a6 a6 a5 a5 a4 a4 a3 a3 a2 a2 a1 a1 a0 d15 to d0 d15 to d0 row address input: a11 to a0 column address input: a10 to a0 figure 6.30 example of 2-cas dram connection 6.6.11 burst operation with dram, in addition to full access (normal access) in which data is accessed by outputting a row address for each access, a fast page mode is also provided which can be used when making consecutive accesses to the same row address. this mode enables fast (burst) access of data by simply changing the column ad dress after the row ad dress has been output. burst access can be selected by setting the be bit to 1 in dramcr. burst access (fast page mode): figures 6.31 and 6.32 show the operation timing for burst access. when there are consecutive access cycles for dram space, the cas signal and column address output cycles (two states) continue as lo ng as the row address is the same for consecutive access cycles. the row address used for the comparison is set w ith bits mxc2 to mxc0 in dramcr. the bus cycle can also be extended in burst access by inserting wait states. the wait state insertion method and timing are the same as for full access. for details, see section 6.6.9, wait control.
rev. 2.00, 03/04, page 133 of 534 t p t r t c1 t c2 t c1 t c2 ( ) read write , ( ) ( ) data bus ( ) ( ) data bus address bus row address column address 1 column address 2 high high figure 6.31 operation timing in fast page mode (rast = 0, cast = 0) t p t r t c1 t c2 t c3 t c1 t c2 t c3 ( ) read write , ( ) ( ) data bus ( ) ( ) data bus address bus row address column address 1 column address 2 high high figure 6.32 operation timing in fast page mode (rast = 0, cast = 1)
rev. 2.00, 03/04, page 134 of 534 ras down mode and ras up mode: even when burst operation is selected, it may happen that access to dram space is not conti nuous, but is interrupted by acce ss to another space. in this case, if the ras signal is held low during the access to the other space, burst operation can be resumed when the same row address in dram space is accessed again. ? ras down mode to select ras down mode, set both the rcdm b it and the be bit to 1 in dramcr. if access to dram space is interrupted and another space is accessed, the ras signal is held low during the access to the other sp ace, and burst access is performed when the row address of the next dram space access is the same as the row address of the previous dram space access. figure 6.33 shows an example of the timing in ras down mode. when the row address for the next dram sp ace access does not match the row address for the previous dram space access and the ras down st ate cannot be continued, one-state ras up cycle (t ru ) is inserted immediately be fore the dram access. figure 6.34 shows an example of the idle cycle insertion when ras down mode is not continued. note, however, that the ras signal will go high if: ? a refresh operation is initiat ed in the ras down state ? self-refreshing is performed ? the chip enters software standby mode ? the rcdm bit or be b it is cleared to 0
rev. 2.00, 03/04, page 135 of 534 normal space read dram space read t p t r t c1 t c2 t 1 t 2 dram space read t c1 t c2 ( ) , ( ) ( ) data bus address bus row address column address 1 high column address 2 external address figure 6.33 example of operation timing in ras down mode (rast = 0, cast = 0) t p t r t p t r t c1 t c2 t c1 t c2 t 1 t 2 t ru ( ) , address bus data bus ( ) row address 1 dram space read dram space read normal space read external address column address 1 row address 2 column address 2 figure 6.34 example of idle cycle insertio n when ras down mode cannot be continued
rev. 2.00, 03/04, page 136 of 534 ? ras up mode to select ras up mode, clear the rcdm bit to 0 in dramcr. each time access to dram space is interrupted and another space is accessed, the ras signal goes high again. burst operation is only performed if dram space is co ntinuous. figure 6.35 shows an example of the timing in ras up mode. normal space read dram space read t p t r t c1 t c2 t c1 t c2 dram space read t 1 t 2 ( ) , ( ) ( ) data bus high address bus row address column address 1 column address 2 external address figure 6.35 example of operation timing in ras up mode (rast = 0, cast = 0)
rev. 2.00, 03/04, page 137 of 534 6.6.12 refresh control this lsi is provided with a dram refresh c ontrol function. cas-before-ras (cbr) refreshing is used. in addition, self-refreshing can be executed when the chip enters the software standby state. refresh control is enabled when area 2 is de signated as dram space in accordance with the setting of bit dset in dramcr. cas-before-ras (c br) refreshing: to select cbr refreshing, set the rfshe bit to 1 in refcr. with cbr refreshing, rtcnt counts up using the input clock selected by bits rtck2 to rtck0 in refcr, and when the count matches the value set in rtcor (compare match), refresh control is performed. at the same time, rtcnt is reset and starts counting up again from h'00. refreshing is thus repeated at fixed intervals determined by rtcor and bits rtck2 to rtck0. set a value in rtcor and bits rtck2 to rtck 0 that will meet the refreshing interval specification for the dram used. when bits rtck2 to rtck0 in refcr are set, rtcnt starts counting up. rtcnt and rtcor settings should therefore be completed before setting bits rtck2 to rtck0. rtcnt operation is shown in figure 6.36, compare match timing in figu re 6.37, and cbr refresh ti ming in figure 6.38. access to external space other than dram space is not possible in pa rallel during the cbr refresh period. rtcor h'00 refresh request rtcnt figure 6.36 rtcnt operation
rev. 2.00, 03/04, page 138 of 534 rtcnt n rtcor n h'00 refresh request signal and cmf bit setting signal figure 6.37 compare match timing t rp ( ) t rr t rc1 t rc2 , figure 6.38 cbr refresh timing a setting can be made in bits rcw1 and rcw0 in refcr to delay ras signal output by one to three cycles. use bits rlw1 and rlw0 in refcr to adjust the width of the ras signal. the settings of bits rcw1, rcw0, rlw1, and rlw0 are valid only in refresh operations. figure 6.39 shows the timing when bits rcw1 and rcw0 are set. t rp ( ) t rrw t rr t rc1 , t rc2 figure 6.39 cbr refresh timing (rcw1 = 0, rcw0 = 1, rlw1 = 0, rlw0 = 0)
rev. 2.00, 03/04, page 139 of 534 self-refreshing: a self-refresh mode (battery backup mode) is provided for dram as a kind of standby mode. in this mode, refresh timing and refresh addresses are generated within the dram. to select self-refreshing, set the rfshe bit and slfrf bit to 1 in refcr. when a sleep instruction is executed to enter software standby mode, the cas and ras signals are output and dram enters self-refresh mode, as shown in figure 6.40. if a cbr refresh request occurs when making a transition to software standby mode, cbr refreshing is executed, then self-refresh mode is entered. t rp t rr , software standby t rc3 ( ) ( ) high figure 6.40 self-refresh timing in some drams provided with a self-refresh mode, the ras signal precharge time immediately after self-refreshing is longer than the normal precharge time. a setting can be made in bits tpcs2 to tpcs0 in refcr to make the precharge time immediately after self-refreshing from 1 to 7 states longer than the normal precharge ti me. in this case, too, normal precharging is performed according to the setti ng of bits tpc1 and tpc0 in draccr, and therefore a setting should be made to give the optimum post-self-refre sh precharge time, including this time. figure 6.41 shows an example of the tim ing when the precharge time imme diately after self-refreshing is extended by 2 states.
rev. 2.00, 03/04, page 140 of 534 dram space write t rc3 t rp1 t rp2 t p t r software standby t c1 t c2 ( ) , ( ) ( ) data bus address bus figure 6.41 example of timing when prechar ge time after self-refreshing is extended by 2 states 6.6.13 dmac single address tr ansfer mode and dram interface when burst mode is selected on the dram interface, the dack output timing can be selected with the dds bit in dramcr. when dram space is accesse d in dmac single address mode at the same time, this bit selects whether or not burst access is to be performed. when dds = 1: burst access is performed by determining the address only, irrespective of the bus master. with the dram interface, the dack output goes low from the t c1 state. figure 6.42 shows the dack output timing for the dram interface when dds = 1.
rev. 2.00, 03/04, page 141 of 534 t p ( ) read write , ( ) ( ) data bus ( ) ( ) data bus address bus t r t c1 t c2 row address column address high high figure 6.42 example of dack output timing when dds = 1 (rast = 0, cast = 0) when dds = 0: when dram space is accessed in dmac single address transfer mode, full access (normal access) is always perform ed. with the dram interface, the dack output goes low from the t r state. in modes other than dmac singl e address transfer mode, burst access can be used when accessing dram space. figure 6.43 shows the dack output timing for the dram interface when dds = 0.
rev. 2.00, 03/04, page 142 of 534 t p ( ) read write , ( ) ( ) data bus ( ) ( ) data bus address bus t r t c1 t c2 t c3 row address column address high high figure 6.43 example of dack output timing when dds = 0 (rast = 0, cast = 1) 6.7 idle cycle 6.7.1 operation when this lsi accesses external address space, it can insert an idle cycle (t i ) between bus cycles in the following three cases: (1) when read accesse s in different areas occur consecutively or when an external access cycle occurs after a single ad dress transfer, (2) when (1) occurs and a write cycle occurs immediately after a read cycle, and (3) when (1) and (2) occur and a read cycle occurs immediately after a write cycle. a condition for idle cycle insertion can be selected with the idle1 and idle0 bits in bcr. the number of id le cycles to be inserted can be set from one to four states by setting the idlc1 and idlc0 bits in bcr. by inserting an idle cycle it is possible, for example, to avoid data collisions between rom, etc., with a long output floating time, and high-speed memory , i/o interfaces, and so on.
rev. 2.00, 03/04, page 143 of 534 consecutive reads in different areas: if consecutive reads in different areas occur while the idle1 and idle0 bits in bcr are set to either b'01, b'10, or b'11, an idle cycle which is set by the idlc1 and idlc0 bits in bcr is inserted at the start of the second read cycle. figure 6.44 shows an example of the operation in th is case. in this example, bus cycle a is a read cycle for rom with a long output floating time, and bus cycle b is a read cycle for sram, each being located in a different area. in (a), an idle cycle is not inserted, and a collision occurs in bus cycle b between the read data from rom and that from sram. in (b), an idle cycle is inserted, and a data collision is prevented. t 1 address bus bus cycle a y data bus t 2 t 3 t 1 t 2 bus cycle b long output floating time data collision (a) no idle cycle insertion (idle1 = 0, idle0 = 0) t 1 address bus bus cycle a data bus t 2 t 3 t i t 1 bus cycle b (b) idle cycle insertion (idle1 = 0, idle0 = 0, idlc1 = 0, idlc0 = 0) t 2 (area a) (area b) (area a) (area b) idle cycle figure 6.44 example of idle cycle operation (consecutive reads in different areas) write after read: if an external write occurs after an external read while the idle1 and idle0 bits in bcr are set to either b'10 or b'11, an id le cycle which is set by the idlc1 and idlc0 bits in bcr is inserted at the start of the write cycle. figure 6.45 shows an example of the operation in th is case. in this example, bus cycle a is a read cycle for rom with a long output floating time, and bus cycle b is a cpu write cycle. in (a), an idle cycle is not inserted, and a collision occurs in bus cycle b between the read data from rom and the cpu write data. in (b), an idle cycle is inserted, and a data collision is prevented.
rev. 2.00, 03/04, page 144 of 534 t 1 address bus bus cycle a data bus t 2 t 3 t 1 t 2 bus cycle b long output floating time data collision t 1 address bus bus cycle a data bus t 2 t 3 t 1 bus cycle b t 2 (area a) (area b) (area a) (area b) y idle cycle t i (a) no idle cycle insertion (idle1 = 0, idle0 = 0) (b) idle cycle insertion (idle1 = 0, idle0 = 0, idlc1 = 0, idlc0 = 0) figure 6.45 example of idle cy cle operation (write after read) read after write: if an external read occurs after an external write while the idle1 and idle0 bits in bcr are set to b'11, an idle cycle which is set by the idlc1 and idlc0 bits in bcr is inserted at the start of the read cycle. figure 6.46 shows an example of the operation in th is case. in this example, bus cycle a is a cpu write cycle and bus cycle b is a read cycle from the sram. in (a), an idle cycle is not inserted, and a collision occurs in bus cycle b between the cpu write data and read data from the sram. in (b), an idle cycle is inserted, and a data collision is prevented.
rev. 2.00, 03/04, page 145 of 534 t 1 address bus bus cycle a data bus t 2 t 3 t 1 t 2 bus cycle b long output floating time data collision t 1 address bus bus cycle a data bus t 2 t 3 t 1 bus cycle b t 2 (area a) (area b) (area a) (area b) y idle cycle t i (a) no idle cycle insertion (idle1 = 0, idle0 = 0) (b) idle cycle insertion (idle1 = 0, idle0 = 0, idlc1 = 0, idlc0 = 0) figure 6.46 example of idle cy cle operation (read after write) relationship between chip select ( cs ) signal and read ( rd ) signal: depending on the system's load conditions, the rd signal may lag behind the cs signal. an exam ple is shown in figure 6.47. in this case, with the setting for no idle cycle insertion (a), there may be a period of overlap between the bus cycle a rd signal and the bus cycle b cs signal. setting idle cycle insertion, as in (b), however, will prevent any overlap between the rd and cs signals. t 1 address bus bus cycle a t 2 t 3 t 1 t 2 bus cycle b overlap period between (area b) and may occur t 1 address bus idle cycle bus cycle a t 2 t 3 t i t 1 bus cycle b t 2 (area a) (area b) (area a) (area b) (a) no idle cycle insertion (idle1 = 0, idle0 = 0) (b) idle cycle insertion (idle1 = 0, idle0 = 0, idlc1 = 0, idlc0 = 0) figure 6.47 relationship between chip select ( cs ) and read ( rd )
rev. 2.00, 03/04, page 146 of 534 idle cycle in case of dram spac e access after normal space access: in a dram space access following a normal space access, the settings of bits idle1, idle0, idlc1, and idlc0 in bcr are valid. however, in the case of consecutive r eads in different areas, for example, if the second read is a full access to dr am space, idle cycles include t p and t i cycles. the timing when a four-state idle cycle is inserted in a full access to dram space is shown in figure 6.48. t 1 address bus external read data bus t 2 t 3 t p t r dram space read t i t i t c1 t c2 figure 6.48 example of dram full ac cess after external read (cast = 0) in burst access in ras down mode, the settings of bits idle1, idle0, idlc1, and idlc0 are valid and an idle cycle is inserted. the timing in this case is illustrated in figure 6.49.
rev. 2.00, 03/04, page 147 of 534 t p address bus , external read idle cycle data bus t r t c1 t c2 t 1 dram space read dram space read t 2 t c2 t 3 t i t c1 figure 6.49 example of idle cy cle operation in ras down mode (consecutive reads in different areas) (idle1 = 0, idle0 = 1, idlc1 = 0, idlc0 = 1, rast = 0, and cast = 0) table 6.7 shows whether there is an idle cycle insertion or not in the case of mixed accesses to normal space and dram space.
rev. 2.00, 03/04, page 148 of 534 table 6.7 idle cycles in mixed acce sses to normal space and dram space previous access next access idlc1 idlc0 idle1 idle0 idle cycle ? ? 0 0 disabled 0 0 0 1 1 0 1 1 state inserted 1 0 1 1 0 1 2 states inserted 1 0 0 1 1 0 1 3 states inserted 1 0 1 1 0 normal/dram space read normal/dram space read (different area) 1 4 states inserted ? ? 0 0 disabled 0 0 0 1 1 0 1 1 state inserted 1 0 1 1 0 1 2 states inserted 1 0 0 1 1 0 1 3 states inserted 1 0 1 1 0 single address transfer external space access 1 4 states inserted
rev. 2.00, 03/04, page 149 of 534 previous access next access idlc1 idlc0 idle1 idle0 idle cycle ? ? 0 0 1 disabled 0 0 1 0 1 1 state inserted 1 1 0 1 2 states inserted 1 0 1 0 1 3 states inserted 1 1 0 normal/dram space read normal/dram space write 1 4 states inserted ? ? 0 0 1 1 0 disabled 0 0 1 1 1 state inserted 1 1 1 2 states inserted 1 0 1 1 3 states inserted normal/dram space write normal/dram space read 1 1 1 4 states inserted 6.7.2 pin states in idle cycle table 6.8 shows the pin states in an idle cycle. table 6.8 pin states in idle cycle pins pin state a19 to a0 contents of following bus cycle d15 to d0 high impedance csn (n = 3 to 0) high * ucas , lcas high as high rd high hwr , lwr high ras high * we high dackn (n = 3 to 0) high note: * remains low in dram space ras down mode.
rev. 2.00, 03/04, page 150 of 534 6.8 write data buffer function this lsi has a write data buffer function for the external data bus. using the write data buffer function enables external writes and dma single addr ess mode transfers to be executed in parallel with internal accesses. the write data buffer f unction is made available by setting the wdbe bit to 1 in bcr. figure 6.50 shows an example of the timing when the write data buffer function is used. when this function is used, if an external address space write or dma single address mode transfer continues for two states or longer, and there is an internal access next, an external write only is executed in the first state, but from the next state onward an internal access (o n-chip memory or internal i/o register read/write) is executed in parallel with th e external address space wr ite rather than waiting until it ends. t 1 internal address bus a19 to a0 external write cycle , t 2 t w t w t 3 on-chip memory read internal i/o register read internal read signal d15 to d0 external address internal memory 1 internal memory 2 external space write internal i/o register address note: n = 3 to 0 figure 6.50 example of timing when write data buffer function is used
rev. 2.00, 03/04, page 151 of 534 6.9 bus arbitration this lsi has a bus arbiter that arbitrates bus master operations (bus arbitration). there are two bus masters ? the cpu and dmac ? that perform read/write operations when they have possession of the bus. each bus master reque sts the bus by means of a bus request signal. the bus arbiter determines priorities at the prescribed timing, and permits use of the bus by means of a bus request acknowledge signal. th e selected bus master then takes possession of the bus and begins its operation. 6.9.1 operation the bus arbiter detects the bus masters? bus request signals, and if the bus is requested, sends a bus request acknowledge signal to the bus master. if there are bus requests from more than one bus master, the bus request acknowledge signal is sent to the one with the highest priority. when a bus master receives the bus request acknowledge signal, it takes possession of the bus until that signal is canceled. the order of priority of the bus master is as follows: (high) dmac > cpu (low) 6.9.2 bus transfer timing even if a bus request is received from a bus master with a higher priority th an that of the bus master that has acquired the bus and is currently operating, the bus is not necessarily transferred immediately. there are specifi c timings at which each bus ma ster can relinquish the bus. cpu: the cpu is the lowest-priority bus master, and if a bus request is received from the dmac, the bus arbiter transfers the bus to the bus master th at issued the request. th e timing for transfer of the bus is as follows: ? the bus is transferred at a break between bus cy cles. however, if a bus cycle is executed in discrete operations, as in the case of a longwor d-size access, the bus is not transferred between the component operations. ? with bit manipulation instructions such as bset and bclr, the sequence of operations is: data read (read), relevant bit manipulation oper ation (modify), write-back (write). the bus is not transferred during this read-m odify-write cycle, which is execut ed as a series of bus cycles. ? if the cpu is in sleep mode, the bus is transferred immediately.
rev. 2.00, 03/04, page 152 of 534 dmac: the dmac sends the bus arbiter a request for the bus when an activation request is generated. in normal transfer mode or in cycle steal transfer m ode, the dmac releases the bus after a single transfer. in block tr ansfer mode, it releases the bus after tran sfer of one block, and in burst mode, after completion of the transfer. 6.10 bus controller operation in reset in a reset, this lsi, including the bus controlle r, enters the reset state immediately, and any executing bus cycle is aborted.
rev. 2.00, 03/04, page 153 of 534 section 7 dma controller (dmac) this lsi has an on-chip dma controller (dmac) which can carry out data transfer on up to 4 channels. 7.1 features ? number of channels: four channels ? address space: physical address space (16-mbyte external space) ? transfer data length: byte, word , or longword can be selected. ? maximum number of transfers: 16,777,215/infinite (free-running) ? address mode: dual address mode or si ngle address mode can be selected. dual address mode addresses of transfer source and transfer destina tion are accessed. values set in the internal dmac register are addresses to be accessed for transfer source and transfer destination. single data transfer re quires two bus cycles. single address mode the peripheral device of transfer source or transfer destination is accessed by the dack signal and another one is accessed by the address. si ngle data transfer requires one bus cycle. ? transfer request: the dmac transfer ac tivation requests are as follows. external request four dreq pins. low-level detection or falling-edge detection can be selected. external requests can be accepted on all channels. auto request a transfer request is automatically generated from the internal dmac. on-chip usb a transfer request can be accepted fr om the on-chip usb on all channels. ? bus mode: cycle steal mode or burst mode can be selected. ? transfer mode: normal mode or block transfer mode can be selected. normal mode single data transfer is performed for single transfer request. the number of tr ansfers is specified as 24 bits (max. 16 mbytes) block transfer mode (only for external request) single block (specified number) data transfer is performed for single transfer request. ? interrupt request: an interrupt request can be sent to the cpu at the end of the specified number of transfers. edma261a_000120020400
rev. 2.00, 03/04, page 154 of 534 ? repeat area set function this function enables data transfer of ring buffer, etc. efficiently because values in the upper bits of the transfer address register are fixe d and address values in the specific range are repeated. repeat area can be set from one bit (t wo bytes) to 23 bits (8 mbytes). repeat area can be set for both transf er source and transfer destination. interrupt request generation can be set by overflow determination of repeat area. ? acceptance of a transfer request and the start of transfer pro cessing can be notified to an external device via the drak pin.
rev. 2.00, 03/04, page 155 of 534 figure 7.1 shows a block diagram of the dmac. n = 0 to 3 dmmdr_n dmacr_n dmtcr_n dmdar_n dmsar_n legend dmsar_n: dmdar_n: dmtcr_n: dmmdr_n: dmacr_n: : : : : dma source address register dma destination address register dma transfer count register dma mode control register dma address control register dma transfer request acceptance acknowledge dma transfer end dma transfer acknowledge address buffer data buffer external pins on-chip usb module internal signals with on-chip usb module interrupt request signals to cpu for individual channels processor bus controller control logic internal data bus module data bus figure 7.1 block diagram of dmac 7.2 input/output pins table 7.1 shows the pin configuration of the dmac. the corresponding port to the dack pin automatically enters the outp ut state by the setting of the single address transfer mode. when the dreq pin is used, the corresponding port must not enter the output state. whether th e corresponding port to the tend / drak pin is used as tend / drak pin can be set by the register.
rev. 2.00, 03/04, page 156 of 534 table 7.1 pin configuration channel name abbre- viation i/o function 0 dma request 0 dreq0 input channel 0 external request dma transfer acknowledge 0 dack0 output channel 0 single address transfer acknowledge dma transfer end 0 tend0 output channel 0 transfer end dreq0 acceptance acknowledge drak0 output notification to external device of channel 0 external request acceptance and start of transfer processing 1 dma request 1 dreq1 input channel 1 external request dma transfer acknowledge 1 dack1 output channel 1 single address transfer acknowledge dma transfer end 1 tend1 output channel 1 transfer end dreq1 acceptance acknowledge drak1 output notification to external device of channel 1 external request acceptance and start of transfer processing 2 dma request 2 dreq2 input channel 2 external request dma transfer acknowledge 2 dack2 output channel 2 single address transfer acknowledge dma transfer end 2 tend2 output channel 2 transfer end dreq2 acceptance acknowledge drak2 output notification to external device of channel 2 external request acceptance and start of transfer processing 3 dma request 3 dreq3 input channel 3 external request dma transfer acknowledge 3 dack3 output channel 3 single address transfer acknowledge dma transfer end 3 tend3 output channel 3 transfer end dreq3 acceptance acknowledge drak3 output notification to external device of channel 3 external request acceptance and start of transfer processing
rev. 2.00, 03/04, page 157 of 534 7.3 register descriptions the dmac has the following registers. ? dma source address register_0 (dmsar_0) ? dma destination address register_0 (dmdar_0) ? dma transfer count re gister_0 (dmtcr_0) ? dma mode control register_0 (dmmdr_0) ? dma address control register_0 (dmacr_0) ? dma source address register_1 (dmsar_1) ? dma destination address register_1 (dmdar_1) ? dma transfer count re gister_1 (dmtcr_1) ? dma mode control register_1 (dmmdr_1) ? dma address control register_1 (dmacr_1) ? dma source address register_2 (dmsar_2) ? dma destination address register_2 (dmdar_2) ? dma transfer count re gister_2 (dmtcr_2) ? dma mode control register_2 (dmmdr_2) ? dma address control register_2 (dmacr_2) ? dma source address register_3 (dmsar_3) ? dma destination address register_3 (dmdar_3) ? dma transfer count re gister_3 (dmtcr_3) ? dma mode control register_3 (dmmdr_3) ? dma address control register_3 (dmacr_3) ? usb transfer control register (ustcr)
rev. 2.00, 03/04, page 158 of 534 7.3.1 dma source addr ess register (dmsar) dmsar is a 32-bit readable/writabl e register that specifies the tran sfer source address. an address update function is provided that updates the register contents to the next transfer source address each time transfer proces sing is performed. in single addres s mode, the dmsar value is ignored when a device with dack is specified as th e transfer source. the upper 8 bits of dmsar are reserved; they are always read as 0 and ca nnot be modified. only 0 should be written to these bits. the dmsar value is undefined at a reset or in hardware standby mode. do not write to dmsar for a channel on which dma transfer is in progress. dmsar can be read at all times by the cpu. when reading dmsar for a channel on which dma transfer processing is in progress, a longword-size read must be executed. 7.3.2 dma destination address register (dmdar) dmdar is a 32-bit readable/writable register that specifies the transfer destination address. an address update function is provided that updates the register contents to the next transfer destination address each time tran sfer processing is performed. in single address mode, the dmdar value is ignored when a device with dack is specified as the transfer destination. the upper 8 bits of dmdar are reserved; they are always read as 0 and ca nnot be modified. only 0 should be written to these bits. the dmdar value is undefined at a re set or in hardware standby mode. do not write to dmdar for a channel on which dma transfer is in progress. dmdar can be read at all times by the cpu. when reading dmdar for a channel on which dma transfer processing is in progress, a longword-size read must be executed. 7.3.3 dma transfer count register (dmtcr) dmtcr specifies the number of transfers. the function differs according to the transfer mode (normal/block). the dmtcr value is undefined at a reset or in hardware standby mode. do not write to dmtcr for a channel on which dma transfer is in progress.
rev. 2.00, 03/04, page 159 of 534 normal transfer mode: bit bit name initial value r/w description 31 to 24 ? all 0 ? reserved these bits are always read as 0. the write value should always be 0. 23 to 0 undefined r/w 24-bit transfer counter these bits specify the numbe r of transfers (number of bytes, word, or longwords). setting h'000001 specifies one transfer. setting h'000000 means no specification for the number of transfers, and the transfer counter function is halted. in this case, there is no transfer end interrupt by the transfe r counter. setting h'ffffff specifies the maximum number of transfers, that is 16,777,215. during dma transfer, this counter shows the remaining number of transfers. this counter can be read at all times. when reading dmtcr for a channel on which dma transfer processing is in progress, a longword-size read must be executed. block transfer mode: bit bit name initial value r/w description 31 to24 ? all 0 ? reserved these bits are always read as 0. the write value should always be 0. 23 to 16 undefined r/w block size these bits specify the block size (number of bytes, words, or longwords) for block transfer. setting h'01 specifies one as the block, while setting h'00 specifies the maximum block size, that is 256. the register value always indicates the specified block size. 15 to 0 undefined r/w 16-bit transfer counter these bits specify the number of block transfers (number of bytes, word, or longwords). setting h'0001 specifies one block transfer. setting h'0000 means no specification for the number of transfers, and the transfer counter function is halted. in this case, there is no transfer end interrupt by the transfer counter. setting h'ffff specifies the maximum number of block transfers, that is 65,535. during dma transfer, this counter shows the remaining number of block transfers.
rev. 2.00, 03/04, page 160 of 534 7.3.4 dma mode control register (dmmdr) dmmdr specifies the operating mode and transfer type. bit bit name initial value r/w description 15 da 0 r/(w) * 1 dma active controls the dma operation. when this bit is set to 1, this indicates that an dma operation is in progress. when auto request mode is specified (by bits mds1 and mds0), transfer processing begins when this bit is set to 1. with external requests, transfer processing begins when a transfer request is issued after this bit has been set to 1. when this bit is cleared to 0 during an dma operation, transfer is halted. if this bit is cleared to 0 during an dma operation in block transfer mode, transfer processing is continued for the currently executing one-block transfer, and the bit is cleared on completion of the currently executing one-block transfer. if an external source that ends (aborts) transfer occurs, this bit is automatically cleared to 0 and transfer is terminated. do not change the operating mode, transfer method, or other parameters while this bit is set to 1. 0: data transfer disabled on corresponding channel [clearing conditions] ? when the specified number of transfers end ? when operation is halted by a repeat area overflow interrupt ? when 0 is written to da while da = 1 (in block transfer mode, write is effective after end of one-block transfer) ? reset, nmi interrupt, hardware standby mode 1: data transfer enabled on corresponding channel and during an dma operation.
rev. 2.00, 03/04, page 161 of 534 bit bit name initial value r/w description 14 bef 0 r/(w) * 2 block transfer error flag flag that indicates the occurrence of an error during block transfer. if an nmi interrupt is generated during block transfer, the dmac immediately terminates the dma operation and sets this bit to 1. the address registers indicate the next transfer addresses during block transfer, but the data for which transfer has been performed within the block size is lost. to clear this bit, 0 should be written after reading 1 from this bit. 0: no block transfer error [clearing condition] writing 0 to bef after reading bef = 1 1: block transfer error and block transfer is abnormal. [setting condition] nmi interrupt during block transfer 13 drake 0 r/w drak pin output enable enables output from the dreq acknowledge/transfer processing start ( drak ) pin. 0: drak pin output disabled 1: drak pin output enabled 12 tende 0 r/w tend pin output enable enables output from the dma transfer end ( tend ) pin. 0: tend pin output disabled 1: tend pin output enabled 11 dreqs 0 r/w dreq select specifies low level sensing or falling edge sensing as the sampling method for the dreq pin used in external request mode. 0: low level sensing (low level sensing is used for the first transfer after transfer is enabled.) 1: falling edge sensing 10 ams 0 r/w address mode select selects single address mode or dual address mode. when single address mode is selected, the dack pin is valid. 0: dual address mode 1: single address mode
rev. 2.00, 03/04, page 162 of 534 bit bit name initial value r/w description mode select 1 and 0 these bits specify the activation source, bus mode, and transfer mode. activation source bus mode transfer mod e 00 auto request cycle steal mode normal transfe r mode 01 auto request burst mode normal transfe r mode 10 external request, on-chip usb cycle steal mode normal transfe r mode 11 external request, on-chip usb cycle steal mode block transfer mode 9 8 mds1 mds0 0 0 r/w r/w note: the transfer from the on-chip usb can be the requested by setting ustcr. see section 7.3.6, usb transfer control register (ustcr). 7 die 0 r/w dma interrupt enable enables or disables interrupt requests. when this bit is set to 1, an interrupt request is generated when the irf bit in dmmdr is set to 1. the interrupt request is cleared by clearing this bit or the irf bit in dmmdr to 0. 0: interrupt request is not generated 1: interrupt request is generated
rev. 2.00, 03/04, page 163 of 534 bit bit name initial value r/w description 6 irf 0 r/(w) * 2 interrupt request flag flag indicating that an interrupt request has occurred and transfer has ended. to clear this bit, the da bit in dmmdr is set to 1 or 0 is written after reading 1 from this bit. 0: no interrupt request [clearing conditions] ? writing 1 to the da bit in dmmdr ? writing 0 to irf after reading irf = 1 1: interrupt request occurrence [setting conditions] ? transfer end interrupt request generated by transfer counter ? source address repeat area overflow interrupt request ? destination address repeat area overflow interrupt request 5 tceie 0 r/w transfer counter end interrupt enable enables or disables transfer end interrupt requests by the transfer counter. when transfer ends according to the transfer counter while this bit is set to 1, the irf bit in dmmdr is set to 1, indicating that an interrupt request has occurred. 0: transfer end interrupt requests by transfer counter are disabled 1: transfer end interrupt requests by transfer counter are enabled 4 sdir 0 r/w single address direction specifies the data transfer direction in single address mode. in dual address mode (ams = 0), the specification by this bit is ignored. 0: transfer direction: dmsar external device with dack 1: transfer direction: external device with dack dmdar
rev. 2.00, 03/04, page 164 of 534 bit bit name initial value r/w description 3 dtsize 0 r/w data transmit size specifies the size of data to be transferred by combination of the lwsize bit. lwsize dtsize 0 0: byte-size (8-bit) specification 0 1: word-size (16-bit) specification 0 0: longword-size (32-bit) specification 1 1: reserved (setting prohibited) 2 ? 0 r/w reserved this bit can be read from or written to. however, the write value should always be 0. 1 lwsize 0 r/w longword data transmit size specifies the size of data to be transferred by combination of the dtsize bit. 0 ? 0 r/w reserved this bit can be read from or written to. however, the write value should always be 0. notes: 1. there is a period when the written va lue is not reflected immediately. 2. only 0 can be written after reading 1, to clear the flag.
rev. 2.00, 03/04, page 165 of 534 7.3.5 dma address control register (dmacr) dmacr specifies address register incrementing/decr ementing and use of the repeat area function. bit bit name initial value r/w description 15 14 sat1 sat0 0 0 r/w r/w source address update mode these bits specify increm enting/decrementing of the transfer source address (dmsar). when an external device with dack is designated as the transfer source in single address mode, the specification by these bits is ignored. 0x: source address (dmsar) is fixed 10: source address is incremented (+1 in byte transfer, +2 in word transfer, or +4 in longword transfer) 11: source address is decremented (?1 in byte transfer, ?2 in word transfer, or ?4 in longword transfer) 13 sarie 0 r/w source address repeat interrupt enable when this bit is set to 1, in the event of source address repeat area overflow, the irf bit in dmmdr is set to 1 and the da bit in dmmdr cleared to 0, and transfer is terminated. if the die bit in dmmdr is 1 when the irf bit in dmmdr is set to 1, an interrupt request is sent to the cpu. when used together with block transfer mode, a source address repeat interrupt is requested at the end of a block-size transfer. if the da bit is set to 1 in dmmdr for the channel on which transfer is terminated by a source address repeat interrupt, transfer can be resumed from the state in which it ended. if a source address repeat area has not been designated, this bit is ignored. 0: source address repeat interrupt is not requested 1: when source address repeat area overflow occurs, the irf bit in dmmdr is set to 1 and an interrupt is requested
rev. 2.00, 03/04, page 166 of 534 bit bit name initial value r/w description 12 11 10 9 8 sara4 sara3 sara2 sara1 sara0 0 0 0 0 0 r/w r/w r/w r/w r/w source address repeat area these bits specify the source address (dmsar) repeat area. the repeat area functi on updates the specified lower address bits, leaving the remaining upper address bits always the same. a repeat area size of 2 bytes to 8 mbytes can be specified. the setting interval is a power-of-two number of bytes. when repeat area overflow results from incrementing or decrementing an address, the lower address is the start address of the repeat area in the case of address incrementing, or the last address of the repeat ar ea in the case of address decrementing. if the sarie bit is set to 1, an interrupt can be requested when repeat area overflow occurs. 00000: not designated source address (dmsar) as repeat area 00001: lower 1 bit (2-byte area) in dmsar designated as repeat area 00010: lower 2 bits (4-byte area) in dmsar designated as repeat area 00011: lower 3 bits (8-byte area) in dmsar designated as repeat area 00100: lower 4 bits (16-byte area) in dmsar designated as repeat area : : 10011: lower 19 bits (512-kbyte area) in dmsar designated as repeat area 10100: lower 20 bits (1-mbyte area) in dmsar designated as repeat area 10101: lower 21 bits (2-mbyte area) in dmsar designated as repeat area 10110: lower 22 bits (4-mbyte area) in dmsar designated as repeat area 10111: lower 23 bits (8-mbyte area) in dmsar designated as repeat area
rev. 2.00, 03/04, page 167 of 534 bit bit name initial value r/w description 7 6 dat1 dat0 0 0 r/w r/w destination address update mode these bits specify increm enting/decrementing of the transfer destination address (dmdar). when an external device with dack is designated as the transfer destination in single address mode, the specification by these bits is ignored. 0x: destination address (dmdar) is fixed 10: destination address is incremented (+1 in byte transfer, +2 in word trans fer, or +4 in longword transfer) 11: destination address is decremented (?1 in byte transfer, ?2 in word transfer, or ?4 in longword transfer) 5 darie 0 r/w destination addr ess repeat interrupt enable when this bit is set to 1, in the event of destination address repeat area overflow the irf bit is set to 1 and the da bit cleared to 0 in dmmdr, and transfer is terminated. if the die bit in dmmdr is 1 when the irf bit in dmmdr is set to 1, an interrupt request is sent to the cpu. when used together with block transfer mode, a destination address repeat interrupt is requested at the end of a block-size transfer. if the da bit is set to 1 in dmmdr for the channel on which transfer is terminated by a destination address repeat interrupt, transfer can be resumed from the state in which it ended. if a destination address repeat area has not been designated, this bit is ignored. 0: destination address repeat interrupt is not requested 1: when destination address repeat area overflow occurs, the irf bit in dmmdr is set to 1 and an interrupt is requested
rev. 2.00, 03/04, page 168 of 534 bit bit name initial value r/w description 4 3 2 1 0 dara4 dara3 dara2 dara1 dara0 0 0 0 0 0 r/w r/w r/w r/w r/w destination address repeat area these bits specify the destination address (dmdar) repeat area. the repeat area function updates the specified lower address bits, leaving the remaining upper address bits always the same. a repeat area size of 2 bytes to 8 mbytes can be specified. the setting interval is a power-of-two number of bytes. when repeat area overflow results from incrementing or decrementing an address, the lower address is the start address of the repeat area in the case of address incrementing, or the last addr ess of the repeat area in the case of address decrementing. if the darie bit is set to 1, an interrupt can be requested when repeat area overflow occurs. 00000: not designated destination address (dmdar) as repeat area 00001: lower 1 bit (2-byte area) in dmdar designated as repeat area 00010: lower 2 bits (4-byte area) in dmdar designated as repeat area 00011: lower 3 bits (8-byte area) designated as repeat area 00100: lower 4 bits (16-byte area) in dmdar designated as repeat area : : 10011: lower 19 bits (512-kbyte area) in dmdar designated as repeat area 10100: lower 20 bits (1-mbyte area) in dmdar designated as repeat area 10101: lower 21 bits (2-mbyte area) in dmdar designated as repeat area 10110: lower 22 bits (4-mbyte area) in dmdar designated as repeat area 10111: lower 23 bits (8-mbyte area) in dmdar designated as repeat area
rev. 2.00, 03/04, page 169 of 534 7.3.6 usb transfer control register (ustcr) ustcr specifies the transfer sour ce from the on-chip usb, etc. bit bit name initial value r/w description 15 ep1dmae 0 r/w endpoint 1 (ep1) dma enable enables a transfer source from the on-chip usb (transfer direction: reading from the on-chip usb (ep1)). when this bit is set to 1, a transfer request from the usb is selected as a transfer source. in block transfer mode, the on-chip usb request must not be set as an activation source. while the da bit in dmmdr is set to 1, the ep1dmae value must not be changed. 0: transfer request from on-chip usb (ep1) not accepted. 1: transfer request from on-chip usb (ep1) accepted. the dreq pin on the corresponding channel is not available. 14 13 urchs1 urchs0 0 0 r/w r/w usb read channel select when the dma transfer is performed by a transfer request from the usb (ep1), these bits select the dmac channel to be used. when the channel which accepts a request is selected and the ep1dmae bit is set to 1, the corresponding channel accepts a usb request rather than an external request. in this case, the transfer direction is reading from the usb (ep1). therefore, the source addres s must be specified as the fifo in the usb (ep1). while the da bit in dmmdr is set to 1, these bits must not be changed. a transfer request from the endpoint 1 (ep1) (reading from the on-chip usb) or a transfer request from the endpoint 2 (ep2) (writing to the on- chip usb) must not be set to the same channel. 00: channel 0 can accept the ep1 transfer request. 01: channel 1 can accept the ep1 transfer request. 10: channel 2 can accept the ep1 transfer request. 11: channel 3 can accept the ep1 transfer request.
rev. 2.00, 03/04, page 170 of 534 bit bit name initial value r/w description 12 ? 0 r/w reserved this bit can be read from or written to. however, the write value should always be 0. 11 ep2dmae 0 r/w endpoint 2 (ep2) dma enable enables a transfer source from the on-chip usb (transfer direction: writing to the on-chip usb). when this bit is set to 1, a transfer request from the usb is selected as a transfer source. in block transfer mode, the on-chip usb request must not be set as an activation source. while the da bit in dmmdr is set to 1, the ep2dmae value must not be changed. 0: transfer request from on-chip usb (ep2) not accepted. 1: transfer request from on-chip usb (ep2) accepted. the dreq pin on the corresponding channel is not available. 10 9 uwchs1 uwchs0 0 0 r/w r/w usb write channel select when the dma transfer is performed by a transfer request from the usb (ep2), these bits select the dmac channel to be used. when the channel which accepts a request is selected and the ep2dmae bit is set to 1, the corresponding channel accepts a usb request rather than an external request. in this case, the transfer direction is writing to the on-chip usb (ep2). therefore, the des tination address must be specified as the fifo in the on-chip usb (ep2). while the da bit in dmmdr is set to 1, these bits must not be changed. a transfer request from the endpoint 1 (ep1) (reading from the on-chip usb) or a transfer request from the endpoint 2 (ep2) (writing to the on- chip usb) must not be set to the same channel. 00: channel 0 can accept the ep2 transfer request. 01: channel 1 can accept the ep2 transfer request. 10: channel 2 can accept the ep2 transfer request. 11: channel 3 can accept the ep2 transfer request. 8 to 0 ? all 0 r/w reserved these bits can be read from or written to. however, the write value should always be 0.
rev. 2.00, 03/04, page 171 of 534 7.4 operation all dmac functions on four channels are common. each mode can be set independently for each channel. the dmac functions can be used by combining each function. 7.4.1 transfer modes the transfer modes of the dmac are summarized in table 7.2. table 7.2 dmac transfer modes address registers address mode transfer mode bus mode transfer origin number of transfers source destination dual address mode normal transfer mode burst/cycle steal mode auto request 1 to 16,777,215 or no specification dmsar dmdar cycle steal mode external request on-chip usb block transfer mode burst transfer of specified block size for a single transfer request block size: 1 to 256 bytes, words, or longwords external request 1 to 65,535 or no specification single address mode ? direct data transfer to/from external device using dack pin instead of source or destination address register ? above transfer mode can be specified in addition to address register setting ? one transfer possible in one bus cycle in single address mode, a transfer request from the on-chip usb is not available. (transfer mode variations are the same as in dual address mode except for a transfer request from the on-chip usb.) dmsar/ dack dack / dmdar
rev. 2.00, 03/04, page 172 of 534 the transfer mode can be set independently for each channel. in normal transfer mode, a one-byte, one-word, or one-longword transfer is executed in response to one transfer request. with auto requests, burst or cycle steal tr ansfer mode can be set. in normal or burst transfer mode, continuous, high-speed transfer can be performed until the specified number of transfers have been executed or the transfer enable b it is cleared to 0. in block tr ansfer mode, a transfer of the specified block size is executed in response to one transfer request. the block size can be from 1 to 256 bytes, words, or longwords. within a block, transfer can be performed at the same high speed as in burst transfer mo de. when the ?no specification? setting (dmtcr = h'000000) is made for the number of tr ansfers, the transfer coun ter is halted and there is no limit on the number of transfers, allowing transfer to be performed endlessly. incrementing or decrementi ng the memory address by 1, 2, or 4, or leaving the address unchanged, can be specified independently for each address regist er. in all transfer modes, it is possible to set a repeat area comprising a pow er-of-two number of bytes. 7.4.2 address modes (dual address mode/single address mode) dual address mode: in dual address mode, both the transfer source and transfer destination are specified by registers in the dmac, and one transfer is executed in two bus cycles. the transfer source address is set in the sour ce address register (dms ar), and the transfer destination address is set in the de stination address register (dmdar). in a transfer operation, the value in external memo ry specified by the tran sfer source address is read in the first bus cycle, and is written to the external memory specified by the transfer destination address in the next bus cycle. these consecutive read and write cycles are indi visible: another bus cycle (external access by an internal bus master or re fresh cycle) does not occu r between these two cycles. tend pin output can be enabled or disabled by means of the tende bit in dmmdr. tend is output for two consecutive bus cycles. the dack signal is not output. figure 7.2 shows an example of the timing in dual address mode.
rev. 2.00, 03/04, page 173 of 534 address bus dma read cycle dma write cycle dmsar dmdar figure 7.2 example of timing in dual address mode single address mode: in single address mode, the dack signal is used instead of the source or destination address register to transfer data di rectly between an extern al device and external memory. in this mode, the dmac accesses the transf er source or transfer destination external device by outputting the external i/o strobe signal ( dack ), and at the same time accesses the other external device in the transfer by outputting an address. in this way, dma transfer can be executed in one bus cycle. in th e example of transfer between ex ternal memory and an external device with dack shown in figure 7.3, data is output to the data bus by the external device and written to external memory in the same bus cycle. the transfer direction, that is whether the external device with dack is the tran sfer source or transfer destination, can be specified with the sdir bit in dmmdr. transfer is performed from the external memory (dmsar) to the external device with dack when sdir = 0, and from the external device with dack to the exte rnal memory (dmdar) when sdir = 1. the setting in the source or destination address register not used in the transfer is ignored. the dack pin becomes valid automatically when single address mode is selected. the dack pin is active-low. tend pin output can be enabled or disabled by means of the tende bit in dmmdr. tend is output for one bus cycle. figure 7.3 shows the data flow in single address mode, and figure 7.4 shows an example of the timing.
rev. 2.00, 03/04, page 174 of 534 microcomputer data flow external address bus external data bus dmac external memory external device with dack figure 7.3 data flow in single address mode
rev. 2.00, 03/04, page 175 of 534 dma cycle dmsar address to external memory space signal to external memory space data output from external memory address bus data bus dma cycle dmdar address to external memory space signal to external memory space address bus transfer from external memory to external device with dack transfer from external device with dack to external memory data bus data output from external device with dack figure 7.4 example of timing in single address mode
rev. 2.00, 03/04, page 176 of 534 7.4.3 dma transfer requests (auto re quest mode/external request mode/usb transfer request) auto request mode: in auto request mode, tr ansfer request signals ar e automatically generated within the dmac in cases where a transfer request signal is not issu ed from outside, such as in transfer between two memories, or between a peripheral module that is not capable of generating transfer requests and memory. in auto request mode, transfer is started when the da bit is set to 1 in dmmdr. in auto request mode, either cycle steal mode or burst mode can be selected as the bus mode. block transfer mode cannot be used. external request mode: in external request mode, transfer is started by a transfer request signal ( dreq ) from a device external to this ls i. dma transfer is started when dreq is input while dma transfer is enabled (da = 1). the transfer request source need not be the data transfer source or data transfer destination. the transfer request signal is accepted via the dreq pin. either falling edge sensing or low level sensing can be selected for the dreq pin by means of the dreqs bit in dmmdr (low level sensing when dreqs = 0, falling edge sensing when dreqs = 1). setting the drake bit to 1 in dmmdr enables a signal confirming transfer request acceptance to be output from the drak pin. the drak signal is output when acceptance and transfer processing has been started in respon se to a single external request. the drak signal enables the external device to determine the timing of dreq signal negation, and makes it possible to provide handshaking between the transfer request source and the dmac. in external request mode, block transfer mode can be used instead of burst mode. block transfer mode allows continuous execution (burst operation) of the specified number of transfers (the block size) in response to a single transfer request. in block transfer mode, the drak signal is output only once for a one-block transfer, since the transfer request via the dreq pin is for a block unit. usb request mode: in usb request mode, dma transfer can be executed by a transfer request from the on-chip usb. when a transfer request from the usb can be accepted and dma transfer is enabled (da = 1), dma transfer is started af ter a transfer request from the usb is input. when a transfer request for the endpoint 1 is accepted, the dmac transfers the endpoint 1 data. when a transfer request for the endpoint 2 is accep ted, the dmac transfers data to the endpoint 2. when a transfer request from the usb is used as a transfer source, single address mode, block transfer mode, and nor mal/burst transfer mode cannot be used.
rev. 2.00, 03/04, page 177 of 534 7.4.4 bus modes (cycle steal mode/burst mode) there are two bus modes: cycle st eal mode and burst mode. when th e activation source is an auto request, either cycle steal mode or burst mode can be selected. when the activation source is an external request, cycle steal mode is used. cycle steal mode: in cycle steal mode, the dmac releases the bus at the end of each transfer of a transfer unit (byte, word, or block). if there is a subsequent transfer request, the dmac takes back the bus, performs another transfer-unit tr ansfer, and then releases the bus again. this procedure is repeated until the tran sfer end condition is satisfied. if a transfer request occurs in another channel during dma transfer, the bus is temporarily released, then transfer is performed on the channel for which the transfer request was issued. if there is no external sp ace bus request from another bus master, a one-cycle bus release interval is inserted. for details on the operation when there ar e requests for a number of channels, see section 7.4.8, channel priority. figure 7.5 shows an example of the timing in cycle steal mode. cpu cpu cpu cpu dmac dmac bus returned temporarily to cpu bus cycle transfer conditions: single address mode, normal transfer mode low level sensing cpu internal bus master is operating in external space figure 7.5 example of timing in cycle steal mode burst mode: in burst mode, once the dmac acquires the bus it continues transferring data, without releasing the bus, until the transfer end condition is satisfied. there is no burst mode in external request mode. in burst mode, once transfer is started it is not interrupted even if there is a transfer request from another channel with higher priority. when the burst mode channel finishes its transfer, it releases the bus in the next cycle in the same way as in cycle steal mode. when the da bit is cleared to 0 in dmmdr, dma transfer is halted. howe ver, dma transfer is executed for all transfer requests generated within the dmac up until the da bit was cleared to 0. if a repeat area overflow interrupt is generated, the da bit is cleared to 0 and transfer is terminated.
rev. 2.00, 03/04, page 178 of 534 figure 7.6 shows an example of the timing in burst mode. cpu cpu cpu cpu bus cycle cpu cycle not generated auto request mode dmac dmac dmac figure 7.6 examples of timing in burst mode 7.4.5 transfer modes (normal transfer mode/block transfer mode) there are two transfer modes: no rmal transfer mode and block transfer mode. when the activation source is an external request, eith er normal transfer mode or block transfer mode can be selected. when the activation source is an auto request, normal transfer mode is used. normal transfer mode: in normal transfer mode , transfer of one transf er unit is processed in response to one transfer request. dmtcr f unctions as a 24-bit transfer counter. the tend signal is output only for the last dma transfer. the drak signal is output each time a transfer request is accepted and tran sfer processing is started. fi gure 7.7 shows examples of dma transfer timing in normal transfer mode. read write read write dma transfer cycle last dma transfer cycle bus cycle (1) dual address mode, auto request mode dma dma bus cycle (2) single address mode, external request mode figure 7.7 examples of timing in normal transfer mode
rev. 2.00, 03/04, page 179 of 534 block transfer mode: in block transfer mode, the number of bytes, words, or longwords specified by the block size is tran sferred in response to one transf er request. the upper 8 bits of dmtcr specify the block size, and the lower 16 bits function as a 16-bit transfer counter. a block size of 1 to 256 can be specified. during transfer of a block, transfer requests for other higher-priority channels are held pending. when transfer of one block is completed, the bus is released in the next cycle. address register values are updated in the same way as in normal mode. there is no function for restoring the initial address register values after each block transfer. the tend signal is output for each block transfer in the dma transfer cycle in which the block ends. the drak signal is output once for one transfer request (for transfer of one block). caution is required when setting the repeat area ove rflow interrupt of the repeat area function in block transfer mode. see section 7.4.6, repeat area function, for details. block transfer is aborted if an nmi interrupt is generated. see section 7.4.12, ending dma transfer, for details. figure 7.8 shows an example of dma transfer timing in block transfer mode. cpu cpu cpu dmac dmac dmac cpu bus cycle cpu cycle not generated one-block transfer cycle transfer conditions: single address mode block size (dmtcr[23:16]) = 3 figure 7.8 example of timing in block transfer mode 7.4.6 repeat area function the dmac has a function for designating a repeat area for source addresses and/or destination addresses. when a repeat area is designated, the address register values repeat within the range specified as the repeat area. norma lly, when a ring buffer is involved in a transfer, an operation is required to restore the address register value to the buffer start address each time the address register value is the last address in the buffer (i.e. when ring buffer address overflow occurs), but if
rev. 2.00, 03/04, page 180 of 534 the repeat area function is used, the operation that restores the address register value to the buffer start address is performed automatically within the dmac. the repeat area function can be set independ ently for the source addr ess register and the destination address register. the source address rep eat area is specified by bits sara4 to sara0 in dmacr, and the destination address repeat area by bits dara4 to dara0 in dmacr. the size of each repeat area can be specified independently. when the address register value is the last addres s in the repeat area an d repeat area overflow occurs, dma transfer can be temporarily halted an d an interrupt request sent to the cpu. if the sarie bit in dmacr is set to 1, when the source address register overflows the repeat area, the irf bit is set to 1 and the da bit cleared to 0 in dmmdr, and transfer is terminated. if die = 1 in dmmdr, an interrupt is requested. if the darie bit in dmacr is set to 1, the above applies to the destination address register. if the da bit in dmmdr is set to 1 during interrupt generation, transfer is resumed. figure 7.9 illustrates the operation of the repeat area function. external memory repeated repeat area overflow interrupt can be requested range of dmsar values h'23fffe h'23ffff h'240000 h'240001 h'240002 h'240003 h'240004 h'240005 h'240006 h'240007 h'240008 h'240009 h'240000 h'240001 h'240002 h'240003 h'240004 h'240005 h'240006 h'240007 : : when lower 3 bits (8-byte area) of dmsar are designated as repeat area (sara4 to sara0 = 3) figure 7.9 example of repe at area function operation
rev. 2.00, 03/04, page 181 of 534 caution is required when the repeat area overflow interrupt function is used together with block transfer mode. if transfer is alwa ys terminated when repeat area ove rflow occurs in block transfer mode, the block size must be a power of two, or a lternatively, the address register value must be set so that the end of a block coincides with the end of the repeat area range. if repeat area overflow occurs while a block is bein g transferred in block transfer mode, the repeat interrupt request is held pending until the end of th e block, and transfer over run will occur. figure 7.10 shows an example in which block transfer mode is used together with the repeat area function. external memory range of dmsar values first block transfer second block transfer h'23fffe h'23ffff h'240000 h'240001 h'240002 h'240003 h'240004 h'240005 h'240006 h'240007 h'240008 h'240009 h'240000 h'240001 h'240002 h'240003 h'240004 h'240005 h'240006 h'240007 h'240000 h'240001 h'240002 h'240003 h'240004 h'240000 h'240001 h'240005 h'240006 h'240007 : : interrupt requested block transfer in progress when lower 3 bits (8-byte area) of dmsar are designated as repeat area (sara4 to sara0 = 3), and block size of 5 (dmtcr[23?16] = 5) is set in block transfer mode figure 7.10 example of repeat area fu nction operation in block transfer mode
rev. 2.00, 03/04, page 182 of 534 7.4.7 registers during dma transfer operation dmac register values are updated as dma transfer processing is performed. the updated values depend on various settings and the transfer status. the following registers and bits are updated: dmsar, dmdar, dmtcr, and bits da, bef, and irf in dmmdr. dma source address register (dmsar): when the dmsar address is accessed as the transfer source, after the dmsa r value is output, dmsar is updated with the address to be accessed next. bits sat1 and sat0 in dmacr specify incrementing or decrementing. the address is fixed when sat1 = 0, incremented when sat1 = 1 and sat0 = 0, and decremented when sat0 = 1. the size of the increment or decrement is determined by the size of the data transferred. when the lwsize and dtsize bits in dmmdr = 0, the data is byte-size and the address is incremented or decremented by 1; when lwsize = 0 and dtsize = 1, the data is word-size and the address is incremented or decremented by 2; when lwsize = 1 and dtsize = 0, the data is longword-size and the address is incremented or decremented by 4. when a repeat area setting is made, the operation co nforms to that setting. the upper part of the address set for the repeat area function is fixed, and is not affected by address updating. when dmsar is read during a transfer opera tion, a longword access must be used. during a transfer operation, dm sar may be updated without regard to accesses from the cpu, and the correct values may not be read if the upper and lower words are read separately. in a longword access, the dmac buffers the dmsar value to ensure that the correct value is output. do not write to dmsar for a channel on wh ich a transfer operat ion is in progress. dma destination address register (dmdar): when the dmdar address is accessed as the transfer destination, after the dmdar value is output, dmdar is updated with the address to be accessed next. bits dat1 and dat0 in dmacr sp ecify incrementing or decrementing. the address is fixed when dat1 = 0, incremented when dat1 = 1 and dat0 = 0, and decremented when dat0 = 1. the size of the increment or decrement is determined by the size of the data transferred. when the lwsize and dtsize bits in dmmdr = 0, the data is byte-size and the address is incremented or decremented by 1; when lwsize = 0 and dtsize = 1, the data is word-size and the address is incremented or decremented by 2; when lwsize = 1 and dtsize = 0, the data is longword-size and the address is incremented or decremented by 4. when a repeat area setting is made, the operation co nforms to that setting. the upper part of the address set for the repeat area function is fixed, and is not affected by address updating. when dmdar is read during a transfer opera tion, a longword access must be used. during a transfer operation, dm dar may be updated without regard to accesses from the cpu, and the
rev. 2.00, 03/04, page 183 of 534 correct values may not be read if the upper and lower words are read separately. in a longword access, the dmac buffers the dmdar value to ensure that the correct value is output. do not write to dmdar for a channel on wh ich a transfer operat ion is in progress. dma transfer count register (dmtcr): when a dma transfer is performed, the value in dmtcr is decremented by 1. however, when the dmtcr value is 0, transfers are not counted and the dmtcr value does not change. dmtcr functions differently in block transfer mode. the upper 8 bits, dmtcr23 to dmtcr16, are used to specify the block size, and their va lue does not change. the lower 16 bits, dmtcr15 to dmtcr0, function as a transfer counter, the value of which is decremented by 1 when a dma transfer is performed. however, when the dmtcr15 to dmtcr0 value is 0, transfers are not counted and the dmtcr15 to dmtcr0 value does not change. in normal transfer mode, all of the lower 24 bits of dmtcr may change, so when dmtcr is read by the cpu during dma transfer, a long word access must be used. during a transfer operation, dmtcr may be updated without rega rd to accesses from the cpu, and the correct values may not be read if the upper and lower words are read separately. in a longword access, the dmac buffers the dmtcr value to ensure that the correct value is output. in block transfer mode, the upper 8 bits are never updated, so there is no problem with using word access. do not write to dmtcr for a channel on whic h a transfer operation is in progress. if there is contention between an address update associated with dma transfer an d a write by the cpu, the cpu write has priority. in the event of contention between an dmtcr update from 1 to 0 and a write (of a nonzero value) by the cpu, the cpu write value has priority as the dmtcr value, but transfer is terminated. transfer does not end if the cpu writes 0 to dmtcr. figure 7.11 shows dmtcr update operations in normal transfer mode and block transfer mode.
rev. 2.00, 03/04, page 184 of 534 23 0 0 dmtcr fixed 23 0 0 before update after update 23 0 1 to h'ffffff dmtcr ?1 23 0 0 to h'fffffe dmtcr dmtcr in normal transfer mode dmtcr in block transfer mode fixed before update after update 23 15 0 16 1 to h'ffff block size dmtcr ?1 23 15 0 16 0 block size 23 15 0 16 0 to h'fffe block size 23 15 0 16 0 block size figure 7.11 dmtcr update operations in normal transfer mode and block transfer mode da bit in dmmdr: the da bit in dmmdr is written to by the cpu to control enabling and disabling of data transfer, but may be cleared automatically by the dmac due to the dma transfer status. there are also pe riods during transfer wh en a 0-write to the da bit by the cpu is not immediately effective. conditions for da bit clearing by the dmac include the following: ? when the dmtcr value changes from 1 to 0, and transfer ends ? when a repeat area overflow interrup t is requested, and transfer ends ? when an nmi interrupt is generated, and transfer halts ? a reset ? hardware standby mode ? when 0 is written to the da bit, and transfer halts when transfer is halted by writing 0 to the da bit, the da bit remains at 1 during the dma transfer period. in block transfer mode, sin ce a block-size transfer is carried out without interruption, the da bit remains at 1 from the time 0 is written to it until the end of the current block-size transfer. in burst mode, transfer is halted for up to thr ee dma transfers following the bus cycle in which 0 is written to the da bit. the da bit remains set to 1 from the time of the 0-write until the end of the last dma cycle. writes (except to the da bit) are prohibited to regi sters of a channel for
rev. 2.00, 03/04, page 185 of 534 which the da bit is set to 1. when changing regist er settings after a 0-write to the da bit, it is necessary to confirm that the da bit has been cleared to 0. figure 7.12 shows the procedure for changing register settings in an operating channel. read da bit write 0 to da bit change register settings da bit = 0? 1 2 3 4 1. write 0 to the da bit in dmmdr. 2. read the da bit. 3. confirm that da = 0. if da = 1, this indicates that dma transfer is in progress. 4. write the required set values to the registers. no yes changing register settings in operating channel register setting changes completed figure 7.12 procedure fo r changing register settings in operating channel bef bit in dmmdr: in block transfer mode, the specified nu mber of transfers (equivalent to the block size) is performed in response to a single tran sfer request. to ensure that the correct number of transfers is carried out, a block-size transfer is always executed, except in the event of a reset, transition to standby mode, or generation of an nmi interrupt. if an nmi interrupt is generated during block transfer, operation is halted midway through a block-size transfer and the da bit is cleared to 0, terminating the transfer operation. in this case the bef bit, which indicates the occurrence of an error during block transfer, is set to 1. irf bit in dmmdr: the irf bit in dmmdr is set to 1 when an interrupt request source occurs. if the die bit in dmmdr is 1 at this time, an interrupt is requested. the timing for setting the irf bit to 1 is when the da bit in dmmdr is cleared to 0 and transfer ends following the end of the dma transfer bus cycle in which the source generating the interrupt occurred. if the da bit is set to 1 and transfer is resumed during interrupt handling, the irf bit is automatically cleared to 0 and the interrupt request is cleared. for details on interrupts, see section 7.5, interrupt sources.
rev. 2.00, 03/04, page 186 of 534 7.4.8 channel priority the priority of the dmac channels is: channel 0 > channel 1 > channel 2> channel 3. table 7.3 shows the dmac channel priority. table 7.3 dmac channel priority channel priority channel 0 high channel 1 channel 2 channel 3 low if transfer requests occur simultaneously for a number of channels, the highest-priority channel according to the priority in tabl e 7.3 is selected for transfer. transfer requests from multip le channels (except auto request cycle steal mode): if transfer requests for different chan nels are issued during a transfer operation, the highest-priority channel (excluding the currently transferring channel) is selected . the selected channel begins transfer after the currently transferring channel releases the bus. if there is a bus request from a bus master other than the dmac at this time, a cycle for the other bus master is initiated. if there is no other bus request, the bus is released for one cycle. channels are not switched during burst transfer or transfer of a block in block transfer mode. figure 7.13 shows an example of the transfer timing when transfer requests occur simultaneously for channels 0, 1, and 2. the example in the figure is for ex ternal request cycle steal mode.
rev. 2.00, 03/04, page 187 of 534 channel 0 transfer idle bus release address bus dma control channel 0 channel 1 channel 1 transfer channel 2 transfer channel 2 channel 0 channel 1 channel 2 channel 0 request held selected request held request held not selected selected channel 1 request cleared request cleared request cleared bus release channel 2 figure 7.13 example of channel priority timing transfer requests from mult iple channels in auto request cycle steal mode: if transfer requests for different channels ar e issued during a transfer in au to request cycle steal mode, the operation depends on the channel priority. if the chan nel that made the transfer request is of higher priority than the channel currently performing tran sfer, the channel that made the transfer request is selected. if the channel that made the transfer request is of lower priority than the channel currently performing tran sfer, that channel's transfer request is held pending, and the currently transferring channel remains selected. the selected channel begins transfer after the curre ntly transferring channel releases the bus. if there is a bus request from a bus master other th an the dmac at this time, a cycle for the other bus master is initiated. if there is no other bus request, the bus is released for one cycle. figure 7.14 shows examples of transfer timing in cases that include auto request cycle steal mode.
rev. 2.00, 03/04, page 188 of 534 channel 0 channel 0 channel 0 channel 1 channel 1 bus conditions (1) channel 0: auto request, cycle steal mode channel 1: external request, cycle steal mode, low level activation channel 0 da bit channel 1/ pin channel 2 channel 2 channel 1 channel 1 channel 2 channel 1 bus conditions (2) channel 1: external request, cycle steal mode, low level activation channel 2: auto request, cycle steal mode channel 1/ pin channel 2 da bit channel 2 channel 2 channel 0 channel 2 channel 0 bus conditions (3) channel 0: auto request, cycle steal mode channel 2: auto request, cycle steal mode * : bus release channel 0 da bit channel 2 da bit * * **** * ** * * ** * * figure 7.14 examples of channel priority timing
rev. 2.00, 03/04, page 189 of 534 7.4.9 dmac bus cycles (dual address mode) normal transfer mode (cycle steal mode): figure 7.15 shows an example of transfer when tend output is enabled, and word-size, normal transfer mode (cycle steal mode) is performed from external 16-bit, 2-state access space to external 16-bit, 2-state access space. dma read dma write dma read dma write dma read dma write address bus bus release bus release bus release bus release last transfer cycle figure 7.15 example of normal transfer mode (cycle steal mode) transfer after one byte, word, or longword has been transferred, the bus is released. while the bus is released, at least one cpu bus cycle is initiated. normal transfer mode (burst mode): figure 7.16 shows an ex ample of transfer when tend output is enabled, and word-size, normal transfer mode (burst mode) is performed from external 16-bit, 2-state access space to exte rnal 16-bit, 2-state access space.
rev. 2.00, 03/04, page 190 of 534 dma read dma write dma read dma write dma read dma write address bus bus release bus release last transfer cycle burst transfer figure 7.16 example of normal transfer mode (burst mode) transfer in burst mode, one-byte, one-word, or one-longword transfers are executed continuously until transfer ends. once burst transfer starts, requests from other channels, even of higher priority, are held pending until transfer ends. if an nmi interrupt is generated while a channe l designated for burst transfer is enabled for transfer, the da bit is cleared and transfer is disabled. if a burst transfer has alr eady been initiated within the dmac, the bus is released on comple tion of the currently executing byte or word transfer, and burst tran sfer is aborted. if the la st transfer cycle in burst transfer has been initiated within the dmac, transfer is executed to the end even if the da bit is cleared. normal transfer mode (cycle stea l mode: transfer source is usb): figure 7.17 shows an example of transfer when usb tr ansfer is enabled, and word-si ze, normal transfer mode (cycle steal mode) is performed from the fifo in the usb to extern al 16-bit, 2-state access space. usb external memory external memory external memory dma read dma write bus release dma read dma write dma read dma write bus release address bus ? usb read (internal signal) usb usb figure 7.17 example of normal transfer mode (cycle steal mode) transfer (transfer source: usb)
rev. 2.00, 03/04, page 191 of 534 after one byte, word, or longword has been transferred, the bus is released. while the bus is released, at least one cpu bus cycle is initiated. normal transfer mode (cycle steal mo de: transfer destination is usb): figure 7.18 shows an example of transf er when usb transfer is en abled, and word-size, norm al transfer mode (cycle steal mode) is performed from external 16-bit, 2-state access space to the fifo in the usb. usb address bus usb write (internal signal) usb usb external memory external memory external memory dma read dma write bus release bus release dma read dma write dma read dma write figure 7.18 example of normal transfer mode (cycle steal mode) transfer (transfer destin ation: usb) after one byte, word, or longword has been transferred, the bus is released. while the bus is released, at least one cpu bus cycle is initiated. block transfer mode (cycle steal mode): figure 7.19 shows an example of transfer when tend output is enabled, and word-size, block transfer mode (cycle steal mode) is performed from external 16-bit, 2-state access space to external 16-bit, 2-state access space. dma read dma write address bus bus release dma read dma write dma read dma write dma read dma write figure 7.19 example of block transfer mode (cycle steal mode) transfer
rev. 2.00, 03/04, page 192 of 534 one block is transferred in response to one transf er request, and after the transfer, the bus is released. while the bus is released, one or more cpu bus cycles are initiated. dreq pin falling edge activation timing: figure 7.20 shows an example of normal mode transfer activ ated by the dreq pin falling edge. dma read dma write address bus write idle bus release transfer destination dma control channel write idle transfer source transfer source bus release dma read dma write bus release request request [1] [3] [2] [4] [5] [6] [7] acceptance resumed acceptance resumed read read idle [1] acceptance after transfer enabling; pin low level is sampled at rise of , and request is held. [2], [5] request is cleared at end of next bus cycle, and activation is started in dmac. [3], [6] dma cycle start; pin high level sampling is started at rise of . [4], [7] when pin high level has been sampled, acceptance is resumed after completion of write cycle. (as in [1], pin low level is sampled at rise of , and request is held.) transfer destination request clearance period request clearance period minimum 3 cycles minimum 3 cycles figure 7.20 example of normal mode transfer activated by dreq pin falling edge dreq pin sampling is performed in each cycle starting at the next rise of after the end of the dmmdr write cycle for setting the transfer-enabled state. when a low level is sampled at the dreq pin while acceptance via the dreq pin is possible, the request is held within the dmac. then when activation is initiated within the dmac, the request is cleared, and dreq pin high level sampling for edge sensing is started. if dreq pin high level sampling is completed by the end of the dma wr ite cycle, acceptance resume s after the end of the write cycle, and dreq pin low level sampling is performed again; this sequence of operations is repeated until the end of the transfer. figure 7.21 shows an example of block transfer mode transfer activated by the dreq pin falling edge.
rev. 2.00, 03/04, page 193 of 534 dma read dma write address bus idle write bus release transfer destination dma control channel write idle transfer source transfer destination transfer source request request minimum 3 cycles acceptance resumed acceptance resumed read bus release dma read dma write bus release one block transfer one block transfer idle [1] [4] [5] [6] [7] [3] [2] [1] acceptance after transfer enabling; pin low level is sampled at rise of , and request is held. [2], [5] request is cleared at end of next bus cycle, and activation is started in dmac. [3], [6] dma cycle start; pin high level sampling is started at rise of . [4], [7] when pin high level has been sampled, acceptance is resumed after completion of dead cycle. (as in [1], pin low level is sampled at rise of , and request is held.) read request clearance period request clearance period minimum 3 cycles figure 7.21 example of block transfer mode transfer activated by dreq pin falling edge dreq pin sampling is performed in each cycle starting at the next rise of after the end of the dmmdr write cycle for setting the transfer-enabled state. when a low level is sampled at the dreq pin while acceptance via the dreq pin is possible, the request is held within the dmac. then when activation is initiated within the dmac, the request is cleared, and dreq pin high level sampling for edge sensing is started. if dreq pin high level sampling is completed by the end of the dma wr ite cycle, acceptance resume s after the end of the write cycle, and dreq pin low level sampling is performed again; this sequence of operations is repeated until the end of the transfer. dreq pin low level activation timing: figure 7.22 shows an example of normal mode transfer activ ated by the dreq pin low level.
rev. 2.00, 03/04, page 194 of 534 dma read dma write address bus idle write idle bus release dma control channel write idle transfer source bus release dma read dma write request read read transfer destination transfer source transfer destination bus release [1] [3] [2] [4] [6] [5] [7] acceptance resumed acceptance resumed [1] acceptance after transfer enabling; pin low level is sampled at rise of , and request is held. [2], [5] request is cleared at end of next bus cycle, and activation is started in dmac. [3], [6] dma cycle is started. [4], [7] acceptance is resumed after completion of write cycle. (as in [1], pin low level is sampled at rise of , and request is held.) minimum 3 cycles request minimum 3 cycles request clearance period request clearance period figure 7.22 example of normal mode transfer activated by dreq pin low level dreq pin sampling is performed in each cycle starting at the next rise of after the end of the dmmdr write cycle for setting the transfer-enabled state. when a low level is sampled at the dreq pin while acceptance via the dreq pin is possible, the request is held within the dmac. then when activation is initiated within the dmac, the request is cleared. at the end of the wr ite cycle, acceptance resumes and dreq pin low level sampling is performed again; this sequence of operations is repeated until the end of the transfer. figure 7.23 shows an example of block transfer mode transfer activated by the dreq pin low level.
rev. 2.00, 03/04, page 195 of 534 dma read dma write address bus idle write bus release dma control channel write idle read bus release dma read dma write one block transfer one block transfer idle transfer destination transfer source transfer destination transfer source [1] [3] [2] [4] [6] [5] [7] acceptance resumed acceptance resumed bus release [1] acceptance after transfer enabling; pin low level is sampled at rise of , and request is held. [2], [5] request is cleared at end of next bus cycle, and activation is started in dmac. [3], [6] dma cycle is started. [4], [7] acceptance is resumed after completion of dead cycle. (as in [1], pin low level is sampled at rise of , and request is held.) minimum 3 cycles request request read minimum 3 cycles request clearance period request clearance period figure 7.23 example of block transfer mode transfer activated by dreq pin low level dreq pin sampling is performed in each cycle starting at the next rise of after the end of the dmmdr write cycle for setting the transfer-enabled state. when a low level is sampled at the dreq pin while acceptance via the dreq pin is possible, the request is held within the dmac. then when activation is initiated within the dmac, the request is cleared. at the end of the wr ite cycle, acceptance resumes and dreq pin low level sampling is performed again; this sequence of operations is repeated until the end of the transfer.
rev. 2.00, 03/04, page 196 of 534 7.4.10 dmac bus cycles (single address mode) single address mode (read): figure 7.24 shows an example of transfer when tend output is enabled, and byte-size, single ad dress mode transfer (read) is performed from external 8-bit, 2- state access space to an external device. address bus bus release bus release bus release last transfer cycle dma read dma read dma read dma read bus release bus release figure 7.24 example of single address mode (byte read) transfer figure 7.25 shows an example of transfer when tend output is enabled, and word-size, single address mode transfer (read) is performed from external 8-bit, 2- state access space to an external device. dma read address bus bus release bus release bus release last transfer cycle bus release dma read dma read figure 7.25 example of single address mode (word read) transfer after one byte or word has been transferred in res ponse to one transfer requ est, the bus is released. while the bus is released, one or more cpu bus cycles are initiated.
rev. 2.00, 03/04, page 197 of 534 figure 7.26 shows an example of transfer when tend output is enabled, and longword-size, single address mode transfer (read ) is performed from external 16 -bit, 2-state access space to an external device. dma read address bus bus release bus release bus release bus release last transfer cycle dma read dma read figure 7.26 example of single address mode (longword read) transfer single address mode (write): figure 7.27 shows an example of transfer when tend output is enabled, and byte-size, single ad dress mode transfer (write) is performed from an external device to external 8-bit, 2-state access space. address bus bus release bus release bus release last transfer cycle dma write dma write dma write dma write bus release bus release figure 7.27 example of single address mode (byte write) transfer figure 7.28 shows an example of transfer when tend output is enabled, and word-size, single address mode transfer (wr ite) is performed from an external de vice to external 8-bit, 2-state access space.
rev. 2.00, 03/04, page 198 of 534 dma write address bus bus release bus release bus release last transfer cycle bus release dma write dma write figure 7.28 example of single address mode (word write) transfer after one byte or word has been transferred in res ponse to one transfer requ est, the bus is released. while the bus is released, one or mo re cpu bus cycles are initiated. figure 7.29 shows an example of transfer when tend output is enabled, and longword-size, single address mode transfer (write) is performed from an external device to external 16-bit, 2- state access space. dma write address bus dma write dma write bus release bus release bus release last transfer cycle bus release figure 7.29 example of single a ddress mode (longword write) transfer
rev. 2.00, 03/04, page 199 of 534 dreq pin falling edge activation timing: figure 7.30 shows an example of single address mode transfer activated by the dreq pin falling edge. dma single address bus idle bus release dma control channel transfer source/ destination transfer source/ destination bus release idle dma single bus release single single idle [1] [3] [2] [4] [6] [5] [7] acceptance resumed acceptance resumed [1] acceptance after transfer enabling; pin low level is sampled at rise of , and request is held. [2], [5] request is cleared at end of next bus cycle, and activation is started in dmac. [3], [6] dma cycle start; pin high level sampling is started at rise of . [4], [7] when pin high level has been sampled, acceptance is resumed after completion of single cycle. (as in [1], pin low level is sampled at rise of , and request is held.) request clearance period request clearance period minimum 3 cycles request minimum 3 cycles request figure 7.30 example of single address mode transfer activated by dreq pin falling edge dreq pin sampling is performed in each cycle starting at the next rise of after the end of the dmmdr write cycle for setting the transfer-enabled state. when a low level is sampled at the dreq pin while acceptance via the dreq pin is possible, the request is held within the dmac. then when activation is initiated within the dmac, the request is cleared, and dreq pin high level sampling for edge sensing is started. if dreq pin high level sampling is completed by the end of the dma single cycle, acceptance re sumes after the end of the single cycle, and dreq pin low level sampling is performed again; this sequence of operations is repeated until the end of the transfer.
rev. 2.00, 03/04, page 200 of 534 dreq pin low level activation timing: figure 7.31 shows an example of single address mode transfer activ ated by the dreq pin low level. single single dma single address bus idle bus release dma control channel transfer source/ destination transfer source/ destination bus release idle dma single bus release idle [1] [3] [2] [4] [6] [5] [7] acceptance resumed acceptance resumed request clearance period request clearance period request request minimum 3 cycles minimum 3 cycles [1] acceptance after transfer enabling; pin low level is sampled at rise of , and request is held. [2], [5] request is cleared at end of next bus cycle, and activation is started in dmac. [3], [6] dma cycle is started. [4], [7] acceptance is resumed after completion of single cycle. (as in [1], pin low level is sampled at rise of , and request is held.) figure 7.31 example of single a ddress mode transfer activated by dreq pin low level dreq pin sampling is performed in each cycle starting at the next rise of after the end of the dmmdr write cycle for setting the transfer-enabled state. when a low level is sampled at the dreq pin while acceptance via the dreq pin is possible, the request is held within the dmac. then when activation is initiated within the dmac, the request is cleared. at the end of the si ngle cycle, acceptance resumes and dreq pin low level sampling is performed again; this sequence of operations is repeated until the end of the transfer.
rev. 2.00, 03/04, page 201 of 534 7.4.11 examples of operation timing in each mode examples of operation timings for various conditions in each mode are shown. the contention with other bus master is described by using the cpu external bus cycle as an example. auto request/cycle steal mode/normal transfer mode: when the da bit is set to 1 in dmmdr, an dma transfer cycle is started a minimum of three cycles later. there is a one-cycle bus release interval between the end of a one-tr ansfer-unit dma cycle and the start of the next transfer. if there is a transfer request for another channel of higher priority, the transfer request by the original channel is held pending, and transfer is performed on the higher-priority channel from the next transfer. transfer on the original channel is resumed on completion of the higher-priority channel transfer. figures 7.32 to 7.34 show operation timing examples for various conditions. ? no contention/dual address mode (see figure 7.32) ? cpu cycles/single address mode (see figure 7.33) ? contention with another channel/single address mode (see figure 7.34) pin bus cycle cpu operation da bit dma read da = 1 write 0 0 1 dma write dma read dma write dma read dma write 3 cycles 1 cycle last transfer cycle sleep bus release bus release bus release figure 7.32 auto request/cycle steal mode/normal transfer mode (no contention/dual address mode)
rev. 2.00, 03/04, page 202 of 534 pin bus cycle cpu operation cpu cycle dma single transfer cycle cpu access cpu cycle cpu cycle cpu cycle 1 bus cycle last transfer cycle dma single transfer cycle dma single transfer cycle cpu access cpu access cpu access figure 7.33 auto request/cycle steal mode/normal transfer mode (cpu cycles/single address mode) pin bus cycle current channel other channel transfer request ( ) dma single cycle 1 cycle 1 cycle 1 cycle higher-priority channel dma cycle dma single cycle dma single cycle dma single cycle bus release bus release bus release bus release bus release figure 7.34 auto request/cycle steal mode/normal transfer mode (contention with another channel/single address mode) auto request/burst mode/normal transfer mode: when the da bit is set to 1 in dmmdr, an dma transfer cycle is started a minimum of three cycles later. once transfer is started, it continues (as a burst) until the tran sfer end condition is satisfied. transfer requests for other channels are held pending until the end of transfer on the current channel.
rev. 2.00, 03/04, page 203 of 534 figures 7.35 to 7.37 show operation timing examples for various conditions. ? cpu cycles/dual address mode (see figure 7.35) ? cpu cycles/single address mode (see figure 7.36) ? contention with another channel/dual address mode (see figure 7.37) pin bus cycle cpu operation da bit dma read dma write dma read dma write dma read dma write cpu access cpu access cpu access 0 1 repeated last transfer cycle cpu cycle cpu cycle cpu cycle figure 7.35 auto request/burst mode/normal transfer mode (cpu cycles/dual address mode) cpu cycle cpu cycle cpu cycle cpu cycle cpu cycle cpu access cpu access cpu access cpu access 1 bus cycle last transfer cycle pin bus cycle cpu operation dma single cycle dma single cycle dma single cycle dma single cycle dma single cycle cpu access figure 7.36 auto request/burst mode/normal transfer mode (cpu cycles/single address mode)
rev. 2.00, 03/04, page 204 of 534 pin bus cycle original channel original channel other channel transfer request ( ) dma single transfer cycle dma single transfer cycle dma single transfer cycle 1 cycle last transfer cycle other channel dma cycle bus release bus release bus release figure 7.37 auto request/burst mode/normal transfer mode (contention with another channel/single address mode) external request/cycle steal mode/normal transfer mode: in external request mode, an dma transfer cycle is started a minimum of three cycles after a transfer request is accepted. the next transfer request is accepted after the end of a one-transfer-un it dma cycle. for external bus space cpu cycles, at least two bus cycles ar e generated before the next dma cycle. if a transfer request is generated for another channel, an dma cycle for the other channel is generated before the next dma cycle. the dreq pin sensing timing is different for low level sensing and falling edge sensing. the same applies to transfer request acceptance and transfer start timing. figures 7.38 to 7.41 show operation timing examples for various conditions. ? no contention/dual address mode/low level sensing (see figure 7.38) ? cpu cycles/single address mode/low level sensing (see figure 7.39) ? no contention/single address mode/falling edge sensing (see figure 7.40) ? contention with another channel/dual address mode/low level sensing (see figure 7.41)
rev. 2.00, 03/04, page 205 of 534 pin bus cycle da bit bus release bus release bus release dma read dma write dma read dma write 0 1 last transfer cycle 3 cycles figure 7.38 external request/cycl e steal mode/normal transfer mode (no contention/dual address mode/low level sensing) pin bus cycle cpu operation last transfer cycle 2 bus cycles cpu cycle cpu access cpu access cpu access cpu access cpu access cpu access dma single transfer cycle dma single transfer cycle cpu cycle cpu cycle cpu cycle cpu cycle cpu cycle figure 7.39 external request/cycl e steal mode/normal transfer mode (cpu cycles/single address mode/low level sensing)
rev. 2.00, 03/04, page 206 of 534 pin bus cycle acceptance internal processing state bus release bus release bus release start of high level sensing start of high level sensing start of high level sensing dma single transfer cycle dma single transfer cycle dma single transfer cycle edge confirmation start of transfer processing edge confirmation start of transfer processing edge confirmation start of transfer processing figure 7.40 external request/cycl e steal mode/normal transfer mode (no contention/single address mode/falling edge sensing) pin original channel original channel other channel other channel bus cycle 3 cycles 1 cycle 1 cycle dma transfer cycle bus release other channel transfer cycle dma read dma write dma read dma write bus release bus release figure 7.41 external request/cycl e steal mode/normal transfer mode (contention with another channel/dual address mode/low level sensing)
rev. 2.00, 03/04, page 207 of 534 external request/cycle steal mode/block transfer mode: in block transfer mode, transfer of one block is performed continuously in the same way as in burst mode. the timing of the start of the next block transfer is the same as in normal tr ansfer mode. if a transfer request is generated for another channel, an dma cycle for the other channe l is generated before the next block transfer. the dreq pin sensing timing is different for low level sensing and falling edge sensing. the same applies to transfer request acceptance and transfer start timing. figures 7.42 to 7.45 show operation timing examples for various conditions. ? no contention/dual address mode/low level sensing (see figure 7.42) ? no contention/single address mode/fallin g edge sensing (see figure 7.43) ? cpu cycles/single address mode/low level sensing (see figure 7.44) ? contention with another channel/dual address mode/low level sensing (see figure 7.45)
rev. 2.00, 03/04, page 208 of 534 pin bus cycle da bit bus release bus release dma read dma write dma read dma write dma read dma write dma read dma write dma read dma write 0 1 last transfer in block 1-block-size transfer period last block last transfer cycle 3 cycles repeated bus release repeated figure 7.42 external request/cycl e steal mode/block transfer mode (no contention/dual address mode/low level sensing)
rev. 2.00, 03/04, page 209 of 534 pin bus cycle bus release bus release last transfer in block 1-block-size transfer period last block last transfer cycle 3 cycles dma single transfer cycle dma single transfer cycle dma single transfer cycle dma single transfer cycle dma single transfer cycle repeated repeated bus release figure 7.43 external request/cycl e steal mode/block transfer mode (no contention/single address mode/falling edge sensing)
rev. 2.00, 03/04, page 210 of 534 pin bus cycle cpu operation 1-block-size transfer period 1-block-size transfer period last transfer in block last transfer in block 2 bus cycles dma single transfer cycle dma single transfer cycle dma single transfer cycle dma single transfer cycle cpu access cpu access cpu access cpu access cpu access cpu cycle cpu cycle cpu cycle cpu cycle cpu cycle cpu cycle cpu access repeated repeated figure 7.44 external request/cycl e steal mode/block transfer mode (cpu cycles/single address mode/low level sensing)
rev. 2.00, 03/04, page 211 of 534 pin bus cycle other channel other channel bus release dma read dma write dma read dma write dma read dma write dma read dma write last transfer in block last transfer in block 1-block-size transfer period 1-block-size transfer period other channel dma cycle bus release bus release repeated repeated figure 7.45 external request/cycl e steal mode/block transfer mode (contention with another channel/dual address mode/low level sensing)
rev. 2.00, 03/04, page 212 of 534 7.4.12 ending dma transfer the operation for ending dma transfer depends on the transfer end conditions. when dma transfer ends, the da bit in dmmdr changes fr om 1 to 0, indicating that dma transfer has ended. transfer end by 1 0 transition of dmtcr: when the value of dmtcr changes from 1 to 0, dma transfer ends on the corr esponding channel and th e da bit in dmmdr is cleared to 0. if the tceie bit in dmmdr is set at this time, a tr ansfer end interrupt request is generated by the transfer counter and the irf bit in dmmdr is set to 1. in block transfer mode, dma transfer ends when the value of bits 15 to 0 in dmtcr changes from 1 to 0. dma transfer does not end if the dmtcr value ha s been 0 since before the start of transfer. transfer end by repeat ar ea overflow interrupt: if an address overflows the repeat area when a repeat area specification has been made an d repeat interrupts have been enabled (with the sarie or darie bit in dmacr), a repeat area overflow interrupt is requested. dma transfer ends, the da bit in dmmdr is cleared to 0, and the irf bit in dmmdr is set to 1. in dual address mode, if a repeat area overflow interrupt is requested dur ing a read cycle, the following write cycle processing is still executed. in block transfer mode, if a repeat area overflow interrupt is requested during transfer of a block, transfer continues to the end of the block. tr ansfer end by means of a repeat area overflow interrupt occurs between block-size transfers. transfer end by 0-write to da bit in dmmdr: when 0 is written to the da bit in dmmdr by the cpu, etc., transfer ends after completion of the dma cycle in which transfer is in progress or a transfer request was accepted. in block transfer mode, dma transfer halts after completion of one-block-size transfer. the da bit in dmmdr is not cleared to 0 until all tr ansfer processing has ended. up to that point, the value of the da bit will be read as 1. transfer abort by nmi interrupt: dma transfer is aborted wh en an nmi interrupt is generated. the da bit is cleared to 0 in all chan nels. in external request mode, dma transfer is performed for all transfer requests for which drak has been output. in dual address mode, processing is executed for the write cycle following the read cycle. in block transfer mode, operation is aborted even in the middle of a block-size transfer. as the transfer is halted midway through a block, the bef bit in dmmdr is set to 1 to indicate that the block transfer was not carried out normally.
rev. 2.00, 03/04, page 213 of 534 when transfer is aborted, register values are reta ined, and as the address registers indicate the next transfer addresses, tran sfer can be resumed by setting the da bit to 1 in dmmdr. if the bef bit is 1 in dmmdr, transfer can be resumed from midway through a block. hardware standby mode and reset input: the dmac is initialized in hardware standby mode and by a reset. dma transfer is not guaranteed in these cases. 7.4.13 relationship between dmac and other bus masters the read and write operations in a dma transfer cycle are indivisible, and a refresh cycle or internal bus master (cpu) access cy cle never occurs between the two. when read and write cycles occur consecutively, as in burst transf er or block transfer, a refresh may be inserted after the write cycle. as the cpu has lower priority than the dmac, the cpu access is not executed until the dmac releases the bus. the dmac releases the bus in the following cases: 1. when dma transfer is performed in cycle steal mode 2. when switching to a different channel 3. when transfer ends in burst transfer mode 4. when transfer of one block ends in block transfer mode 7.5 interrupt sources dmac interrupt sources are a transfer end indicat ed by the transfer counter, and repeat area overflow interrupts. table 7.4 shows the interrupt sources and their priority. table 7.4 interrupt sou rces and priority order interrupt interrupt sour ce interrupt priority dmtend0 transfer end indicated by channel 0 transfer counter channel 0 source address repeat area overflow channel 0 destination address repeat area overflow high dmtend1 transfer end indicated by channel 1 transfer counter channel 1 source address repeat area overflow channel 1 destination address repeat area overflow dmtend2 transfer end indicated by channel 2 transfer counter channel 2 source address repeat area overflow channel 2 destination address repeat area overflow dmtend3 transfer end indicated by channel 3 transfer counter channel 3 source address repeat area overflow channel 3 destination address repeat area overflow low
rev. 2.00, 03/04, page 214 of 534 interrupt sources can be enabled or disabled by means of the die bit in dmmdr for the relevant channel, and can be sent to the interrupt controller independently. the relative priority of the channels is determined by the interrupt controller (see table 7.4). figure 7.46 shows the transfer end interrupt logic. a transfer end interrupt is generated whenever the die bit is set to 1 while the irf bit is set to 1 in dmmdr. transfer end interrupt irf bit die bit figure 7.46 transfer end interrupt logic interrupt source settings are made individually with the interrupt enable bits in the registers for the relevant channels. the transfer co unter's transfer end interrupt is enabled or disabled by means of the tceie bit in dmmdr, the sour ce address register repeat area overflow interrupt by means of the sarie bit in dmacr, and the destination address register repeat area overflow interrupt by means of the darie bit in dmacr. when an in terrupt source occurs while the corresponding interrupt enable bit is set to 1, the irf bit in dmmdr is set to 1. the irf bit is set by all interrupt sources indiscriminately. the transfer end interrupt can be cleared either by clearing the ir f bit to 0 in dmmdr within the interrupt handling routine, or by re-setting the transfer counter and address registers and then setting the da bit to 1 in dmmdr to perform transfer continuation processing. an example of the procedure for cl earing the transfer end interrupt and restarting transfer is shown in figure 7.47.
rev. 2.00, 03/04, page 215 of 534 [1] write set values to the registers (transfer counter, address registers, etc.). [2] write 1 to the da bit in dmmdr to restart dma operation. when 1 is written to the da bit, the irf bit in dmmdr is automatically cleared to 0 and the interrupt source is cleared. [3] the interrupt handling routine is ended with an rte instruction, etc. [4] clear the irf bit to 0 in dmmdr by first reading 1 from it, then writing 0. [5] after the interrupt handling routine is ended with an rte instruction, etc., interrupt masking is cleared. [6] write set values to the registers (transfer counter, address registers, etc.). [7] write 1 to the da bit in dmmdr to restart dma operation. end of transfer restart processing write 1 to da bit change register settings end of interrupt handling routine clear irf bit to 0 transfer restart after end of interrupt handling routine transfer end interrupt exception handling routine transfer continuation processing change register settings write 1 to da bit end of interrupt handling routine (rte instruction execution) end of transfer restart processing [1] [4] [5] [6] [7] [2] [3] figure 7.47 example of procedure for restarting transfer on channel in which transfer end interrupt occurred
rev. 2.00, 03/04, page 216 of 534 7.6 usage notes dmac register access during operation: except for clearing the da bit to 0 in dmmdr, settings should not be changed for a channel in operation (including the transfer standby state). transfer must be disabled before changing a setting for an operational channel. module stop state: when the dmackstp bit is set to 1 in mstpcr, the dmac clock stops and the dmac enters the module stop state. however, 1 cannot be written to the dmackstp bit when any of the dmac's channels is enabled for transfer, or when an interrupt is being requested. before setting the dmackstp bit, first clear the da bit in dmmdr to 0, then clear the irf or die bit in dmmdr to 0. when the dmac clock stops, dmac registers ca n no longer be accessed. the following dmac register settings remain valid in the module stop state, and so should be changed, if necessary, before making the module stop transition. ? tende = 1 in dmmdr ( tend pin enable) ? drake = 1 in dmmdr ( drak pin enable) ? ams = 1 in dmmdr ( dack pin enable) dreq pin falling edge activation: falling edge sensing on the dreq pin is performed in synchronization with dmac internal operations, as indicated below. [1] activation request standby state: waits for low level sensing on dreq pin, then goes to [2]. [2] transfer standby state: waits for dmac data tr ansfer to become possibl e, then goes to [3]. [3] activation request disabled state: waits for high level sensing on dreq pin, then goes to [1]. after dmac transfer is enabled, the dmac goes to state [1], so low level sensing is used for the initial activation after tr ansfer is enabled. activation source acceptance: at the start of activation sour ce acceptance, low level sensing is used for both falling edge sensing and low level sensing on the dreq pin. therefore, a request is accepted in the case of a low level at the dreq pin that occurs before execution of the dmmdr write for setting the transfer-enabled state. when the dmac is activated, make sure, if nece ssary, that a low level do es not remain at the dreq pin from the previous end of transfer, etc. enabling interrupt requests when irf = 1 in dmmdr: when transfer is started while the irf bit is set to 1 in dmmdr, if the die bit is set to 1 in dmmdr together with the da bit in dmmdr, enabling interrupt requests, an interrupt will be requested since die = 1 and irf = 1. to prevent the occurrence of an er roneous interrupt request when tr ansfer starts, ensure that the irf bit is cleared to 0 before the die bit is set to 1.
rev. 2.00, 03/04, page 217 of 534 source address/destination address: when transfer data size is sp ecified as word or longword, an even (word) value or value multiplied by four (longword) must be set in dmsar and dmdar. when transfer data size is spec ified as word and an odd value is set in dmsar or dmdar, the lowest bit of the address is regarded as 0 and accessed. when transfer data size is specified as longword and a value not multiplied by four is set in dmsar or dmdar, the lowest two bits of th e address are regarded as 0 and accessed.
rev. 2.00, 03/04, page 218 of 534
rev. 2.00, 03/04, page 219 of 534 section 8 i/o ports table 8.1 summarizes the port functions. the pins of each port also have other functions such as input/output or interrupt input pins of on-chip peripheral modules. each i/o port includes a data direction register (ddr) that controls input/output, a data register (dr) that stores output data, and a port register (port) us ed to read the pin states. ports 1 to 4 can drive a single ttl load and 30 pf capacity load. ports 5 to 9, and a can drive a single ttl load and 50 pf capacity load. all of the i/o ports can drive a darlington transistor when outputting data. ports 3 (p34, p35), 5 (p52, p53, p56, p57), 7, and a (pa0, pa1) are schmitt-triggered inputs when used as the irq input. port 3 (p32, p33) is a schmitt-triggered input when the software standby state is entered by using the usb.
rev. 2.00, 03/04, page 220 of 534 table 8.1 port functions port description extended mode (expe = 1) single-chip mode (expe = 0) port 1 general i/o port also functioning as usb2 i/o p17/usd15 p16/usd14 p15/usd13 p14/usd12 p13/usd11 p12/usd10 p11/usd9 p10/usd8 p17/usd15 p16/usd14 p15/usd13 p14/usd12 p13/usd11 p12/usd10 p11/usd9 p10/usd8 port 2 general i/o port also functioning as usb2 i/o and dmac i/o p27/usd7/ drak1 p26/usd6/ dack1 p25/usd5/ tend1 p24/usd4/ dreq1 p23/usd3/ drak0 p22/usd2/ dack0 p21/usd1/ tend0 p20/usd0/ dreq0 p27/usd7/ drak1 p26/usd6/ dack1 p25/usd5/ tend1 p24/usd4/ dreq1 p23/usd3/ drak0 p22/usd2/ dack0 p21/usd1/ tend0 p20/usd0/ dreq0 port 3 general i/o port also functioning as usb2 i/o and interrupt input p37/usopm1 p36/usopm0 p35/( irq5 )/vbus p34/( irq4 )/ustxv p33/uslsta1 p32/uslsta0 p31/usclk p30/uswdvld p37/usopm1 p36/usopm0 p35/( irq5 )/vbus p34/( irq4 )/ustxv p33/uslsta1 p32/uslsta0 p31/usclk p30/uswdvld port 4 general i/o port also functioning as usb2 i/o p47/usxcvrs p46/ustxrdy p45/ustsel p44/ ussusp p43/usrxv p42/usrxerr p41/usrxact p40/ usrst p47/usxcvrs p46/ustxrdy p45/ustsel p44/ ussusp p43/usrxv p42/usrxerr p41/usrxact p40/ usrst
rev. 2.00, 03/04, page 221 of 534 port description extended mode (expe = 1) single-chip mode (expe = 0) port 5 general i/o port also functioning as external data bus i/o, dmac i/o, and interrupt input p57/d7/( irq7 )/ drak3 p56/d6/( irq6 )/ dack3 p55/d5/ tend3 p54/d4/ dreq3 p53/d3/( irq3 )/ drak2 p52/d2/( irq2 )/ dack2 p51/d1/ tend2 p50/d0/ dreq2 p57/( irq7 )/ drak3 p56/( irq6 )/ dack3 p55/ tend3 p54/ dreq3 p53/( irq3 )/ drak2 p52/( irq2 )/ dack2 p51/ tend2 p50/ dreq2 port 6 general i/o port also functioning as external address bus output and timer i/o p67/a15 p66/a14/tmo1 p65/a13/tmri1 p64/a12/tmci1 p63/a11 p62/a10/tmo0 p61/a9/tmri0 p60/a8/tmci0 p67 p66/tmo1 p65/tmri1 p64/tmci1 p63 p62/tmo0 p61/tmri0 p60/tmci0 port 7 general i/o port also functioning as external address bus output and interrupt input p77/a7/ irq7 p76/a6/ irq6 p75/a5/ irq5 p74/a4/ irq4 p73/a3/ irq3 p72/a2/ irq2 p71/a1/ irq1 p70/a0/ irq0 p77/ irq7 p76/ irq6 p75/ irq5 p74/ irq4 p73/ irq3 p72/ irq2 p71/ irq1 p70/ irq0 port 8 general i/o port also functioning as external data bus i/o p87/d15 p86/d14 p85/d13 p84/d12 p83/d11 p82/d10 p81/d9 p80/d8 p87 p86 p85 p84 p83 p82 p81 p80
rev. 2.00, 03/04, page 222 of 534 port description extended mode (expe = 1) single-chip mode (expe = 0) port 9 general i/o port also functioning as external bus control output p97/ p96/ as p95/ rd p94/ hwr p93/ lwr p92/ cs2 / ras p91/ cs1 p90/ cs0 p97/ p96 p95 p94 p93 p92 p91 p90 port a general i/o port also functioning as external address bus output, external bus control output, and interrupt input pa3/a19/ cs3 pa2/a18/ ucas pa1/a17/ lcas /( irq1 ) pa0/a16/( irq0 ) pa3 pa2 pa1/( irq1 ) pa0/( irq0 ) 8.1 port 1 port 1 is an 8-bit i/o port that also has other functions. the port 1 has the following registers. ? port 1 data direction register (p1ddr) ? port 1 data register (p1dr) ? port 1 register (port1) 8.1.1 port 1 data di rection register (p1ddr) the individual bits of p1ddr specify input or output for the pins of port 1. p1ddr cannot be read; if it is, an undefined value will be read. bit bit name initial value r/w description 7 6 5 4 3 2 1 0 p17ddr p16ddr p15ddr p14ddr p13ddr p12ddr p11ddr p10ddr 0 0 0 0 0 0 0 0 w w w w w w w w when a pin function is specified to a general purpose i/o, setting this bit to 1 ma kes the corresponding port 1 pin an output pin, while clearing this bit to 0 makes the pin an input pin.
rev. 2.00, 03/04, page 223 of 534 8.1.2 port 1 data register (p1dr) p1dr stores output data for the port 1 pins. bit bit name initial value r/w description 7 6 5 4 3 2 1 0 p17dr p16dr p15dr p14dr p13dr p12dr p11dr p10dr 0 0 0 0 0 0 0 0 r/w r/w r/w r/w r/w r/w r/w r/w output data for a pin is stored when the pin function is specified to a general purpose output. 8.1.3 port 1 register (port1) port1 shows the pin states of the port 1. port1 cannot be modified. bit bit name initial value r/w description 7 6 5 4 3 2 1 0 p17 p16 p15 p14 p13 p12 p11 p10 ? * ? * ? * ? * ? * ? * ? * ? * r r r r r r r r if a port1 read is performed while p1ddr bits are set to 1, the p1dr values are read. if a port1 read is performed while p1ddr bits are cleared to 0, the pin states are read. note: * determined by the states of pins p17 to p10.
rev. 2.00, 03/04, page 224 of 534 8.1.4 pin functions port 1 pins also function as the pins for us b i/o. the correspondence between the register specification and the pin functions is shown below. ? p17/usd15 the pin function is switched as shown below according to the combination of the p17ddr bit and the usbckstp bit in mstpcrl. usbckstp 1 0 p17ddr 0 1 ? pin function p17 input p17 output usd15 i/o ? p16/usd14 the pin function is switched as shown below acc ording to the combination of the p16ddr bit and the usbckstp bit in mstpcrl. usbckstp 1 0 p16ddr 0 1 ? pin function p16 input p16 output usd14 i/o ? p15/usd13 the pin function is switched as shown below acc ording to the combination of the p15ddr bit and the usbckstp bit in mstpcrl. usbckstp 1 0 p15ddr 0 1 ? pin function p15 input p15 output usd13 i/o ? p14/usd12 the pin function is switched as shown below acc ording to the combination of the p14ddr bit and the usbckstp bit in mstpcrl. usbckstp 1 0 p14ddr 0 1 ? pin function p14 input p14 output usd12 i/o
rev. 2.00, 03/04, page 225 of 534 ? p13/usd11 the pin function is switched as shown below according to the combination of the p13ddr bit and the usbckstp bit in mstpcrl. usbckstp 1 0 p13ddr 0 1 ? pin function p13 input p13 output usd11 i/o ? p12/usd10 the pin function is switched as shown below according to the combination of the p12ddr bit and the usbckstp bit in mstpcrl. usbckstp 1 0 p12ddr 0 1 ? pin function p12 input p12 output usd10 i/o ? p11/usd9 the pin function is switched as shown below according to the combination of the p11ddr bit and the usbckstp bit in mstpcrl. usbckstp 1 0 p11ddr 0 1 ? pin function p11 input p11 output usd9 i/o ? p10/usd8 the pin function is switched as shown below according to the combination of the p10ddr bit and the usbckstp bit in mstpcrl. usbckstp 1 0 p10ddr 0 1 ? pin function p10 input p10 output usd8 i/o
rev. 2.00, 03/04, page 226 of 534 8.2 port 2 port 2 is an 8-bit i/o port that also has other functions. the port 2 has the following registers. ? port 2 data direction register (p2ddr) ? port 2 data register (p2dr) ? port 2 register (port2) 8.2.1 port 2 data di rection register (p2ddr) the individual bits of p2ddr specify input or output for the pins of port 2. p2ddr cannot be read; if it is, an undefined value will be read. bit bit name initial value r/w description 7 6 5 4 3 2 1 0 p27ddr p26ddr p25ddr p24ddr p23ddr p22ddr p21ddr p20ddr 0 0 0 0 0 0 0 0 w w w w w w w w when a pin function is specified to a general purpose i/o, setting this bit to 1 ma kes the corresponding port 2 pin an output pin, while clearing this bit to 0 makes the pin an input pin. 8.2.2 port 2 data register (p2dr) p2dr stores output data for the port 2 pins. bit bit name initial value r/w description 7 6 5 4 3 2 1 0 p27dr p26dr p25dr p24dr p23dr p22dr p21dr p20dr 0 0 0 0 0 0 0 0 r/w r/w r/w r/w r/w r/w r/w r/w output data for a pin is stored when the pin function is specified to a general purpose output.
rev. 2.00, 03/04, page 227 of 534 8.2.3 port 2 register (port2) port2 shows the pin states of the port 2. port2 cannot be modified. bit bit name initial value r/w description 7 6 5 4 3 2 1 0 p27 p26 p25 p24 p23 p22 p21 p20 ? * ? * ? * ? * ? * ? * ? * ? * r r r r r r r r if a port2 read is performed while p2ddr bits are set to 1, the p2dr values are read. if a port2 read is performed while p2ddr bits are cleared to 0, the pin states are read. note: * determined by the states of pins p27 to p20. 8.2.4 pin functions port 2 pins also function as the pins for dmac i/o and usb i/o. the correspondence between the register specification and the pin functions is shown below. ? p27/usd7/ drak1 the pin function is switched as shown below according to the combination of the p27ddr bit, the drake bit in dmmdr_1, and the usbckstp bit in mstpcrl. usbckstp 1 0 drake 0 1 ? p27ddr 0 1 ? ? pin function p27 input p27 output drak1 output usd7 i/o ? p26/usd6/ dack1 the pin function is switched as shown below according to the combination of the p26ddr bit, the ams bit in dmmdr_1, the expe bit in mdcr, and the usbckstp bit in mstpcrl. usbckstp 1 0 expe 0 1 ? ams ? 0 1 ? p26ddr 0 1 0 1 ? ? pin function p26 input p26 output p26 input p26 output dack1 output usd6 i/o
rev. 2.00, 03/04, page 228 of 534 ? p25/usd5/ tend1 the pin function is switched as shown below acc ording to the combination of the p25ddr bit, the tende bit in dmmdr_1, and the usbckstp bit in mstpcrl. usbckstp 1 0 tende 0 1 ? p25ddr 0 1 ? ? pin function p25 input p25 output tend1 output usd5 i/o ? p24/usd4/ dreq1 the pin function is switched as shown below acc ording to the combination of the p24ddr bit, the dreqs bit in dmmdr_1, and the usbckstp bit in mstpcrl. usbckstp 1 0 p24ddr 0 1 ? p24 input p24 output usd4 i/o pin function dreq1 input * note: * when dreqs = 1, this pin functions as dreq1 input. ? p23/usd3/ drak0 the pin function is switched as shown below according to the combination of the p23ddr bit, the drake bit in dmmdr_0, and the usbckstp bit in mstpcrl. usbckstp 1 0 drake 0 1 ? p23ddr 0 1 ? ? pin function p23 input p23 output drak0 output usd3 i/o ? p22/usd2/ dack0 the pin function is switched as shown below according to the combination of the p22ddr bit, the ams bit in dmmdr_0, the expe bit in mdcr, and the usbckstp bit in mstpcrl. usbckstp 1 0 expe 0 1 ? ams ? 0 1 ? p22ddr 0 1 0 1 ? ? pin function p22 input p 22 output p22 input p22 output dack0 output usd2 i/o
rev. 2.00, 03/04, page 229 of 534 ? p21/usd1/ tend0 the pin function is switched as shown below according to the combination of the p21ddr bit, the tende bit in dmmdr_0, and the usbckstp bit in mstpcrl. usbckstp 1 0 tende 0 1 ? p21ddr 0 1 ? ? pin function p21 input p21 output tend0 output usd1 i/o ? p20/usd0/ dreq0 ? the pin function is switched as shown below according to the combination of the p20ddr bit, the dreqs bit in dmmdr_0, and the usbckstp bit in mstpcrl. usbckstp 1 0 p20ddr 0 1 ? p20 input p20 output usd0 i/o pin function dreq0 input * note: * when dreqs = 1, this pin functions as dreq0 input.
rev. 2.00, 03/04, page 230 of 534 8.3 port 3 port 3 is an 8-bit i/o port that also has other functions. the port 3 has the following registers. ? port 3 data direction register (p3ddr) ? port 3 data register (p3dr) ? port 3 register (port3) 8.3.1 port 3 data di rection register (p3ddr) the individual bits of p3ddr specify input or output for the pins of port 3. p3ddr cannot be read; if it is, an undefined value will be read. bit bit name initial value r/w description 7 6 5 4 3 2 1 0 p37ddr p36ddr p35ddr p34ddr p33ddr p32ddr p31ddr p30ddr 0 0 0 0 0 0 0 0 w w w w w w w w when a pin function is specified to a general purpose i/o, setting this bit to 1 ma kes the corresponding port 3 pin an output pin, while clearing this bit to 0 makes the pin an input pin. 8.3.2 port 3 data register (p3dr) p3dr stores output data for the port 3 pins. bit bit name initial value r/w description 7 6 5 4 3 2 1 0 p37dr p36dr p35dr p34dr p33dr p32dr p31dr p30dr 0 0 0 0 0 0 0 0 r/w r/w r/w r/w r/w r/w r/w r/w output data for a pin is stored when the pin function is specified to a general purpose output.
rev. 2.00, 03/04, page 231 of 534 8.3.3 port 3 register (port3) port3 shows the pin states of the port 3. port3 cannot be modified. bit bit name initial value r/w description 7 6 5 4 3 2 1 0 p37 p36 p35 p34 p33 p32 p31 p30 ? * ? * ? * ? * ? * ? * ? * ? * r r r r r r r r if a port3 read is performed while p3ddr bits are set to 1, the p3dr values are read. if a port3 read is performed while p3ddr bits are cleared to 0, the pin states are read. note: * determined by the states of pins p37 to p30. 8.3.4 pin functions port 3 pins also function as the pins for usb i/o and interrupt input. the correspondence between the register specification and the pin functions is shown below. ? p37/usopm1 the pin function is switched as shown below according to the combination of the p37ddr bit and the usbckstp bit in mstpcrl. usbckstp 1 0 p37ddr 0 1 ? pin function p37 input p37 output usopm1 output ? p36/usopm0 the pin function is switched as shown below according to the combination of the p36ddr bit and the usbckstp bit in mstpcrl. usbckstp 1 0 p36ddr 0 1 ? pin function p36 input p36 output usopm0 output
rev. 2.00, 03/04, page 232 of 534 ? p35/( irq5 )/usvbus the pin function is switched as shown below acc ording to the combination of the p35ddr bit, the usbckstp bit in mstpcrl, and the iss5 bit in issr. usbckstp 1 0 p35ddr 0 1 ? p35 input p35 output usvbus input pin function irq5 interrupt input * note: * when iss5 = 1, this pin functions as irq5 interrupt input. ? p34/( irq4 )/ustxv the pin function is switched as shown below according to the combination of the p34ddr bit, the usbckstp bit in mstpcrl, and the iss4 bit in issr. usbckstp 1 0 p34ddr 0 1 ? p34 input p34 output ustxv output pin function irq4 interrupt input * note: * when iss4 = 1, this pin functions as irq4 interrupt input. ? p33/uslsta1 the pin function is switched as shown below acc ording to the combination of the p33ddr bit and the usbckstp bit in mstpcrl. usbckstp 1 0 p33ddr 0 1 ? pin function p33 input p33 output uslsta1 input ? p32/uslsta0 the pin function is switched as shown below according to the combination of the p32ddr bit and the usbckstp bit in mstpcrl. usbckstp 1 0 p32ddr 0 1 ? pin function p32 input p32 output uslsta0 input
rev. 2.00, 03/04, page 233 of 534 ? p31/usclk the pin function is switched as shown below according to the combination of the p31ddr bit and the usbckstp bit in mstpcrl. usbckstp 1 0 p31ddr 0 1 ? pin function p31 input p31 output usclk input ? p30/uswdvld the pin function is switched as shown below according to the combination of the p30ddr bit and the usbckstp bit in mstpcrl. usbckstp 1 0 p30ddr 0 1 ? pin function p30 input p30 output uswdvld i/o 8.4 port 4 port 4 is an 8-bit i/o port that also has other functions. the port 4 has the following registers. ? port 4 data direction register (p4ddr) ? port 4 data register (p4dr) ? port 4 register (port4) 8.4.1 port 4 data di rection register (p4ddr) the individual bits of p4ddr specify input or output for the pins of port 4. p4ddr cannot be read; if it is, an undefined value will be read. bit bit name initial value r/w description 7 6 5 4 3 2 1 0 p47ddr p46ddr p45ddr p44ddr p43ddr p42ddr p41ddr p40ddr 0 0 0 0 0 0 0 0 w w w w w w w w when a pin function is specified to a general purpose i/o, setting this bit to 1 ma kes the corresponding port 4 pin an output pin, while clearing this bit to 0 makes the pin an input pin.
rev. 2.00, 03/04, page 234 of 534 8.4.2 port 4 data register (p4dr) p4dr stores output data for the port 4 pins. bit bit name initial value r/w description 7 6 5 4 3 2 1 0 p47dr p46dr p45dr p44dr p43dr p42dr p41dr p40dr 0 0 0 0 0 0 0 0 r/w r/w r/w r/w r/w r/w r/w r/w output data for a pin is stored when the pin function is specified to a general purpose output. 8.4.3 port 4 register (port4) port4 shows the pin states of the port 4. port4 cannot be modified. bit bit name initial value r/w description 7 6 5 4 3 2 1 0 p47 p46 p45 p44 p43 p42 p41 p40 ? * ? * ? * ? * ? * ? * ? * ? * r r r r r r r r if a port4 read is performed while p4ddr bits are set to 1, the p4dr values are read. if a port4 read is performed while p4ddr bits are cleared to 0, the pin states are read. note: * determined by the states of pins p47 to p40.
rev. 2.00, 03/04, page 235 of 534 8.4.4 pin functions port 4 pins also function as the pins for us b i/o. the correspondence between the register specification and the pin functions is shown below. ? p47/usxcvrs the pin function is switched as shown below according to the combination of the p47ddr bit and the usbckstp bit in mstpcrl. usbckstp 1 0 p47ddr 0 1 ? pin function p47 input p47 output usxcvrs output ? p46/ustxrdy the pin function is switched as shown below according to the combination of the p46ddr bit and the usbckstp bit in mstpcrl. usbckstp 1 0 p46ddr 0 1 ? pin function p46 input p46 output ustxrdy input ? p45/ustsel the pin function is switched as shown below according to the combination of the p45ddr bit and the usbckstp bit in mstpcrl. usbckstp 1 0 p45ddr 0 1 ? pin function p45 input p45 output ustsel output ? p44/ ussusp the pin function is switched as shown below according to the combination of the p44ddr bit and the usbckstp bit in mstpcrl. usbckstp 1 0 p44ddr 0 1 ? pin function p44 input p44 output ussusp output
rev. 2.00, 03/04, page 236 of 534 ? p43/usrxv the pin function is switched as shown below acc ording to the combination of the p43ddr bit and the usbckstp bit in mstpcrl. usbckstp 1 0 p43ddr 0 1 ? pin function p43 input p43 output usrxv input ? p42/usrxerr the pin function is switched as shown below according to the combination of the p42ddr bit and the usbckstp bit in mstpcrl. usbckstp 1 0 p42ddr 0 1 ? pin function p42 input p42 output usrxerr input ? p41/usrxact the pin function is switched as shown below according to the combination of the p41ddr bit and the usbckstp bit in mstpcrl. usbckstp 1 0 p41ddr 0 1 ? pin function p41 input p41 output usrxact input ? p40/ usrst the pin function is switched as shown below acc ording to the combination of the p40ddr bit and the usbckstp bit in mstpcrl. usbckstp 1 0 p40ddr 0 1 ? pin function p40 input p40 output usrst output
rev. 2.00, 03/04, page 237 of 534 8.5 port 5 port 5 is an 8-bit i/o port that also has other functions. the port 5 has the following registers. ? port 5 data direction register (p5ddr) ? port 5 data register (p5dr) ? port 5 register (port5) 8.5.1 port 5 data di rection register (p5ddr) the individual bits of p5ddr specify input or output for the pins of port 5. p5ddr cannot be read; if it is, an undefined value will be read. bit bit name initial value r/w description 7 6 5 4 3 2 1 0 p57ddr p56ddr p55ddr p54ddr p53ddr p52ddr p51ddr p50ddr 0 0 0 0 0 0 0 0 w w w w w w w w when a pin function is specified to a general purpose i/o, setting this bit to 1 ma kes the corresponding port 5 pin an output pin, while clearing this bit to 0 makes the pin an input pin. 8.5.2 port 5 data register (p5dr) p5dr stores output data for the port 5 pins. bit bit name initial value r/w description 7 6 5 4 3 2 1 0 p57dr p56dr p55dr p54dr p53dr p52dr p51dr p50dr 0 0 0 0 0 0 0 0 r/w r/w r/w r/w r/w r/w r/w r/w output data for a pin is stored when the pin function is specified to a general purpose output.
rev. 2.00, 03/04, page 238 of 534 8.5.3 port 5 register (port5) port5 shows the pin states of the port 5. port5 cannot be modified. bit bit name initial value r/w description 7 6 5 4 3 2 1 0 p57 p56 p55 p54 p53 p52 p51 p50 ? * ? * ? * ? * ? * ? * ? * ? * r r r r r r r r if a port5 read is performed while p5ddr bits are set to 1, the p5dr values are read. if a port5 read is performed while p5ddr bits are cleared to 0, the pin states are read. note: * determined by the states of pins p57 to p50. 8.5.4 pin functions port 5 pins also function as the pins for external data bus i/o, dmac i/o, and interrupt input. the correspondence between the register specification and the pin functions is shown below. ? p57/d7/( irq7 )/ drak3 the pin function is switched as shown below acc ording to the combination of the p57ddr bit, the drake bit in dmmdr_3, the expe bit in mdcr, and the iss7 bit in issr. expe 0 1 bus mode ? all areas are 8-bit space at least one area is 16-bit space drake 0 0 1 ? p57ddr 0 1 0 1 ? ? p57 input p57 output p57 input p57 output drak3 output d7 i/o pin function irq7 interrupt input * note: * when iss7 = 1, this pin functions as irq7 interrupt input.
rev. 2.00, 03/04, page 239 of 534 ? p56/d6/( irq6 )/ dack3 the pin function is switched as shown below according to the combination of the p56ddr bit, the ams bit in dmmdr_3, the expe bit in mdcr, and the iss6 bit in issr. expe 0 1 bus mode ? all areas are 8-bit space at least one area is 16-bit space ams 0 0 1 ? p56ddr 0 1 0 1 ? ? p56 input p56 output p56 input p56 output dack3 output d6 i/o pin function irq6 interrupt input * note: * when iss6 = 1, this pin functions as irq6 interrupt input. ? p55/d5/ tend3 the pin function is switched as shown below according to the combination of the p55ddr bit, the tende bit in dmmdr_3, and the expe bit in mdcr. expe 0 1 bus mode ? all areas are 8-bit space at least one area is 16-bit space tende 0 0 1 ? p55ddr 0 1 0 1 ? ? pin function p55 input p55 output p55 input p55 output tend3 output d5 i/o ? p54/d4/ dreq3 the pin function is switched as shown below according to the combination of the p54ddr bit, the dreqs bit in dmmdr_3, and the expe bit in mdcr. expe 0 1 bus mode ? all areas are 8-bit space at least one area is 16-bit space p54ddr 0 1 0 1 ? p54 input p54 output p54 input p54 output d4 i/o pin function dreq3 input * note: * when dreqs = 1, this pin functions as dreq3 input.
rev. 2.00, 03/04, page 240 of 534 ? p53/d3/( irq3 )/ drak2 the pin function is switched as shown below acc ording to the combination of the p53ddr bit, the drake bit in dmmdr_2, the expe bit in mdcr, and the iss3 bit in issr. expe 0 1 bus mode ? all areas are 8-bit space at least one area is 16-bit space drake 0 0 1 ? p53ddr 0 1 0 1 ? ? p53 input p53 output p53 input p53 output drak2 output d3 i/o pin function irq3 interrupt input * note: * when iss3 = 1, this pin functions as irq3 interrupt input. ? p52/d2/( irq2 )/ dack2 the pin function is switched as shown below according to the combination of the p52ddr bit, the ams bit in dmmdr_2, the expe bit in mdcr, and the iss2 bit in issr. expe 0 1 bus mode ? all areas are 8-bit space at least one area is 16-bit space ams 0 0 1 ? p52ddr 0 1 0 1 ? ? p52 input p52 output p52 input p52 output dack2 output d2 i/o pin function irq2 interrupt input * note: * when iss2 = 1, this pin functions as irq2 interrupt input.
rev. 2.00, 03/04, page 241 of 534 ? p51/d1/ tend2 the pin function is switched as shown below according to the combination of the p51ddr bit, the tende bit in dmmdr_2, and the expe bit in mdcr. expe 0 1 bus mode ? all areas are 8-bit space at least one area is 16-bit space tende 0 0 1 ? p51ddr 0 1 0 1 ? ? pin function p51 input p51 output p51 input p51 output tend2 output d1 i/o ? p50/d0/ dreq2 the pin function is switched as shown below according to the combination of the p50ddr bit, the dreqs bit in dmmdr_2, and the expe bit in mdcr. expe 0 1 bus mode ? all areas are 8-bit space at least one area is 16-bit space p50ddr 0 1 0 1 ? p50 input p50 output p50 input p50 output d0 i/o pin function dreq2 input * note: * when dreqs = 1, this pin functions as dreq2 input.
rev. 2.00, 03/04, page 242 of 534 8.6 port 6 port 6 is an 8-bit i/o port that also has other functions. the port 6 has the following registers. ? port 6 data direction register (p6ddr) ? port 6 data register (p6dr) ? port 6 register (port6) 8.6.1 port 6 data di rection register (p6ddr) the individual bits of p6ddr specify input or output for the pins of port 6. p6ddr cannot be read; if it is, an undefined value will be read. bit bit name initial value r/w description 7 6 5 4 3 2 1 0 p67ddr p66ddr p65ddr p64ddr p63ddr p62ddr p61ddr p60ddr 0 0 0 0 0 0 0 0 w w w w w w w w when a pin function is specified to a general purpose i/o, setting this bit to 1 ma kes the corresponding port 6 pin an output pin, while clearing this bit to 0 makes the pin an input pin. 8.6.2 port 6 data register (p6dr) p6dr stores output data for the port 6 pins. bit bit name initial value r/w description 7 6 5 4 3 2 1 0 p67dr p66dr p65dr p64dr p63dr p62dr p61dr p60dr 0 0 0 0 0 0 0 0 r/w r/w r/w r/w r/w r/w r/w r/w output data for a pin is stored when the pin function is specified to a general purpose output.
rev. 2.00, 03/04, page 243 of 534 8.6.3 port 6 register (port6) port6 shows the pin states of the port 6. port6 cannot be modified. bit bit name initial value r/w description 7 6 5 4 3 2 1 0 p67 p66 p65 p64 p63 p62 p61 p60 ? * ? * ? * ? * ? * ? * ? * ? * r r r r r r r r if a port6 read is performed while p6ddr bits are set to 1, the p6dr values are read. if a port6 read is performed while p6ddr bits are cleared to 0, the pin states are read. note: * determined by the states of pins p67 to p60. 8.6.4 pin functions port 6 pins also function as the pins for external address bus output and timer i/o. the correspondence between the register specification and the pin functions is shown below. ? p67/a15 the pin function is switched as shown below according to the combination of the p67ddr bit, the expe bit in mdcr, and the amoe bit in pfcr1. expe 0 1 amoe ? 0 1 p67ddr 0 1 0 1 ? pin function p67 input p67 outpu t p67 input p67 output a15 output
rev. 2.00, 03/04, page 244 of 534 ? p66/a14/tmo1 the pin function is switched as shown below acc ording to the combination of the p66ddr bit, the expe bit in mdcr, the amoe bit in pfcr1, and the os3 to os0 bits in tcsr_1. expe 0 1 amoe ? 0 1 os3 to os0 all 0 not all 0 all 0 not all 0 ? p66ddr 0 1 ? 0 1 ? ? pin function p66 input p66 output tmo1 output p66 input p66 output tmo1 output a14 output ? p65/a13/tmri1 the pin function is switched as shown below acc ording to the combination of the p65ddr bit, the expe bit in mdcr, and the amoe bit in pfcr1. expe 0 1 amoe ? 0 1 p65ddr 0 1 0 1 ? p65 input p65 output p65 in put p65 output a13 output pin function tmri1 input * note: * when used as a tmr counter reset, set the cclr1 and cclr0 bits in tcr_1 to 11. ? p64/a12/tmci1 the pin function is switched as shown below according to the combination of the p64ddr bit, the expe bit in mdcr, and the amoe bit in pfcr1. expe 0 1 amoe ? 0 1 p64ddr 0 1 0 1 ? p64 input p64 output p64 in put p64 output a12 output pin function tmci1 input * note: * when used as an external clock input pin of tmr, select the external clock by bits cks2 to cks0 in tcr_1.
rev. 2.00, 03/04, page 245 of 534 ? p63/a11 the pin function is switched as shown below according to the combination of the p63ddr bit, the expe bit in mdcr, and the amoe bit in pfcr1. expe 0 1 amoe ? 0 1 p63ddr 0 1 0 1 ? pin function p63 input p63 outpu t p63 input p63 output a11 output ? p62/a10/tmo0 the pin function is switched as shown below according to the combination of the p62ddr bit, the expe bit in mdcr, the amoe bit in pfcr1, and the os3 to os0 bits in tcsr_0. expe 0 1 amoe ? 0 1 os3 to os0 all 0 not all 0 all 0 not all 0 ? p62ddr 0 1 ? 0 1 ? ? pin function p62 input p62 output tmo0 output p62 input p62 output tmo0 output a10 output ? p61/a9/tmri0 the pin function is switched as shown below according to the combination of the p61ddr bit, the expe bit in mdcr, and the amoe bit in pfcr1. expe 0 1 amoe ? 0 1 p61ddr 0 1 0 1 ? p61 input p61 output p61 in put p61 output a9 output pin function tmri0 input * note: * when used as a tmr counter reset, set the cclr1 and cclr0 bits in tcr_0 to 11.
rev. 2.00, 03/04, page 246 of 534 ? p60/a8/tmci0 the pin function is switched as shown below acc ording to the combination of the p60ddr bit, the expe bit in mdcr, and the amoe bit in pfcr1. expe 0 1 amoe ? 0 1 p60ddr 0 1 0 1 ? p60 input p60 output p60 in put p60 output a8 output pin function tmci0 input * note: * when used as an external clock input pin of tmr, select the external clock by bits cks2 to cks0 in tcr_0. 8.7 port 7 port 7 is an 8-bit i/o port that also has other functions. the port 7 has the following registers. ? port 7 data direction register (p7ddr) ? port 7 data register (p7dr) ? port 7 register (port7) 8.7.1 port 7 data di rection register (p7ddr) the individual bits of p7ddr specify input or output for the pins of port 7. p7ddr cannot be read; if it is, an undefined value will be read. bit bit name initial value r/w description 7 6 5 4 3 2 1 0 p77ddr p76ddr p75ddr p74ddr p73ddr p72ddr p71ddr p70ddr 0 0 0 0 0 0 0 0 w w w w w w w w when a pin function is specified to a general purpose i/o, setting this bit to 1 ma kes the corresponding port 7 pin an output pin, while clearing this bit to 0 makes the pin an input pin.
rev. 2.00, 03/04, page 247 of 534 8.7.2 port 7 data register (p7dr) p7dr stores output data for the port 7 pins. bit bit name initial value r/w description 7 6 5 4 3 2 1 0 p77dr p76dr p75dr p74dr p73dr p72dr p71dr p70dr 0 0 0 0 0 0 0 0 r/w r/w r/w r/w r/w r/w r/w r/w output data for a pin is stored when the pin function is specified to a general purpose output. 8.7.3 port 7 register (port7) port7 shows the pin states of the port 7. port7 cannot be modified. bit bit name initial value r/w description 7 6 5 4 3 2 1 0 p77 p76 p75 p74 p73 p72 p71 p70 ? * ? * ? * ? * ? * ? * ? * ? * r r r r r r r r if a port7 read is performed while p7ddr bits are set to 1, the p7dr values are read. if a port7 read is performed while p7ddr bits are cleared to 0, the pin states are read. note: * determined by the states of pins p77 to p70.
rev. 2.00, 03/04, page 248 of 534 8.7.4 pin functions port 7 pins also function as the pins for external address bus output and interrupt input. the correspondence between the register specification and the pin functions is shown below. ? p77/a7/ irq7 the pin function is switched as shown below acc ording to the combination of the p77ddr bit, the expe bit in mdcr, the aloe bit in pfcr1, and the iss7 bit in issr. expe 0 1 aloe ? 0 1 p77ddr 0 1 0 1 ? p77 input p77 output p77 in put p77 output a7 output pin function irq7 interrupt input * note: * when iss7 = 0, this pin functions as irq7 interrupt input. ? p76/a6/ irq6 the pin function is switched as shown below acc ording to the combination of the p76ddr bit, the expe bit in mdcr, the aloe bit in pfcr1, and the iss6 bit in issr. expe 0 1 aloe ? 0 1 p76ddr 0 1 0 1 ? p76 input p76 output p76 in put p76 output a6 output pin function irq6 interrupt input * note: * when iss6 = 0, this pin functions as irq6 interrupt input. ? p75/a5/ irq5 the pin function is switched as shown below acc ording to the combination of the p75ddr bit, the expe bit in mdcr, the aloe bit in pfcr1, and the iss5 bit in issr. expe 0 1 aloe ? 0 1 p75ddr 0 1 0 1 ? p75 input p75 output p75 in put p75 output a5 output pin function irq5 interrupt input * note: * when iss5 = 0, this pin functions as irq5 interrupt input.
rev. 2.00, 03/04, page 249 of 534 ? p74/a4/ irq4 the pin function is switched as shown below according to the combination of the p74ddr bit, the expe bit in mdcr, the aloe bit in pfcr1, and the iss4 bit in issr. expe 0 1 aloe ? 0 1 p74ddr 0 1 0 1 ? p74 input p74 output p74 in put p74 output a4 output pin function irq4 interrupt input * note: * when iss4 = 0, this pin functions as irq4 interrupt input. ? p73/a3/ irq3 the pin function is switched as shown below according to the combination of the p73ddr bit, the expe bit in mdcr, the aloe bit in pfcr1, and the iss3 bit in issr. expe 0 1 aloe ? 0 1 p73ddr 0 1 0 1 ? p73 input p73 output p73 in put p73 output a3 output pin function irq3 interrupt input * note: * when iss3 = 0, this pin functions as irq3 interrupt input. ? p72/a2/ irq2 the pin function is switched as shown below according to the combination of the p72ddr bit, the expe bit in mdcr, the aloe bit in pfcr1, and the iss2 bit in issr. expe 0 1 aloe ? 0 1 p72ddr 0 1 0 1 ? p72 input p72 output p72 in put p72 output a2 output pin function irq2 interrupt input * note: * when iss2 = 0, this pin functions as irq2 interrupt input.
rev. 2.00, 03/04, page 250 of 534 ? p71/a1/ irq1 the pin function is switched as shown below acc ording to the combination of the p71ddr bit, the expe bit in mdcr, the aloe bit in pfcr1, and the iss1 bit in issr. expe 0 1 aloe ? 0 1 p71ddr 0 1 0 1 ? p71 input p71 output p71 in put p71 output a1 output pin function irq1 interrupt input * note: * when iss1 = 0, this pin functions as irq1 interrupt input. ? p70/a0/ irq0 the pin function is switched as shown below according to the combination of the p70ddr bit, the expe bit in mdcr, the aloe bit in pfcr1, and the iss0 bit in issr. expe 0 1 aloe ? 0 1 p70ddr 0 1 0 1 ? p70 input p70 output p70 in put p70 output a0 output pin function irq0 interrupt input * note: * when iss0 = 0, this pin functions as irq0 interrupt input.
rev. 2.00, 03/04, page 251 of 534 8.8 port 8 port 8 is an 8-bit i/o port that also has other functions. the port 8 has the following registers. ? port 8 data direction register (p8ddr) ? port 8 data register (p8dr) ? port 8 register (port8) 8.8.1 port 8 data di rection register (p8ddr) the individual bits of p8ddr specify input or output for the pins of port 8. p8ddr cannot be read; if it is, an undefined value will be read. bit bit name initial value r/w description 7 6 5 4 3 2 1 0 p87ddr p86ddr p85ddr p84ddr p83ddr p82ddr p81ddr p80ddr 0 0 0 0 0 0 0 0 w w w w w w w w when a pin function is specified to a general purpose i/o, setting this bit to 1 ma kes the corresponding port 8 pin an output pin, while clearing this bit to 0 makes the pin an input pin. 8.8.2 port 8 data register (p8dr) p8dr stores output data for the port 8 pins. bit bit name initial value r/w description 7 6 5 4 3 2 1 0 p87dr p86dr p85dr p84dr p83dr p82dr p81dr p80dr 0 0 0 0 0 0 0 0 r/w r/w r/w r/w r/w r/w r/w r/w output data for a pin is stored when the pin function is specified to a general purpose output.
rev. 2.00, 03/04, page 252 of 534 8.8.3 port 8 register (port8) port8 shows the pin states of the port 8. port8 cannot be modified. bit bit name initial value r/w description 7 6 5 4 3 2 1 0 p87 p86 p85 p84 p83 p82 p81 p80 ? * ? * ? * ? * ? * ? * ? * ? * r r r r r r r r if a port8 read is performed while p8ddr bits are set to 1, the p8dr values are read. if a port8 read is performed while p8ddr bits are cleared to 0, the pin states are read. note: * determined by the states of pins p87 to p80. 8.8.4 pin functions port 8 pins also function as the pins for extern al data bus i/o. the co rrespondence between the register specification and the pin functions is shown below. ? p87/d15 the pin function is switched as shown below acc ording to the combination of the p87ddr bit and the expe bit in mdcr. expe 0 1 p87ddr 0 1 ? pin function p87 input p87 output d15 i/o ? p86/d14 the pin function is switched as shown below acc ording to the combination of the p86ddr bit and the expe bit in mdcr. expe 0 1 p86ddr 0 1 ? pin function p86 input p86 output d14 i/o
rev. 2.00, 03/04, page 253 of 534 ? p85/d13 the pin function is switched as shown below according to the combination of the p85ddr bit and the expe bit in mdcr. expe 0 1 p85ddr 0 1 ? pin function p85 input p85 output d13 i/o ? p84/d12 the pin function is switched as shown below according to the combination of the p84ddr bit and the expe bit in mdcr. expe 0 1 p84ddr 0 1 ? pin function p84 input p84 output d12 i/o ? p83/d11 the pin function is switched as shown below according to the combination of the p83ddr bit and the expe bit in mdcr. expe 0 1 p83ddr 0 1 ? pin function p83 input p83 output d11 i/o ? p82/d10 the pin function is switched as shown below according to the combination of the p82ddr bit and the expe bit in mdcr. expe 0 1 p82ddr 0 1 ? pin function p82 input p82 output d10 i/o ? p81/d9 the pin function is switched as shown below according to the combination of the p81ddr bit and the expe bit in mdcr. expe 0 1 p81ddr 0 1 ? pin function p81 input p81 output d9 i/o
rev. 2.00, 03/04, page 254 of 534 ? p80/d8 the pin function is switched as shown below acc ording to the combination of the p80ddr bit and the expe bit in mdcr. expe 0 1 p80ddr 0 1 ? pin function p80 input p80 output d8 i/o 8.9 port 9 port 9 is an 8-bit i/o port that also has other functions. the port 9 has the following registers. ? port 9 data direction register (p9ddr) ? port 9 data register (p9dr) ? port 9 register (port9) 8.9.1 port 9 data di rection register (p9ddr) the individual bits of p9ddr specify input or output for the pins of port 9. p9ddr cannot be read; if it is, an undefined value will be read. bit bit name initial value r/w description 7 6 5 4 3 2 1 0 p97ddr p96ddr p95ddr p94ddr p93ddr p92ddr p91ddr p90ddr 0 0 0 0 0 0 0 0 w w w w w w w w when a pin function is specified to a general purpose i/o, setting this bit to 1 ma kes the corresponding port 9 pin an output pin, while clearing this bit to 0 makes the pin an input pin.
rev. 2.00, 03/04, page 255 of 534 8.9.2 port 9 data register (p9dr) p9dr stores output data for the port 9 pins. bit bit name initial value r/w description 7 6 5 4 3 2 1 0 p97dr p96dr p95dr p94dr p93dr p92dr p91dr p90dr 0 0 0 0 0 0 0 0 r/w r/w r/w r/w r/w r/w r/w r/w output data for a pin is stored when the pin function is specified to a general purpose output. 8.9.3 port 9 register (port9) port9 shows the pin states of the port 9. port9 cannot be modified. bit bit name initial value r/w description 7 6 5 4 3 2 1 0 p97 p96 p95 p94 p93 p92 p91 p90 ? * ? * ? * ? * ? * ? * ? * ? * r r r r r r r r if a port9 read is performed while p9ddr bits are set to 1, the p9dr values are read. if a port9 read is performed while p9ddr bits are cleared to 0, the pin states are read. note: * determined by the states of pins p97 to p90.
rev. 2.00, 03/04, page 256 of 534 8.9.4 pin functions port 9 pins also function as the pins for external bus control output. the correspondence between the register specification and the pin functions is shown below. ? p97/ the pin function is switched as shown below acc ording to the combination of the p97ddr bit and the ckoe bit in pfcr1. ckoe 0 1 p97ddr 0 1 ? pin function p97 input p97 output output ? p96/ as the pin function is switched as shown below acc ording to the combination of the p96ddr bit and the expe bit in mdcr. expe 0 1 p96ddr 0 1 ? pin function p96 input p96 output as output ? p95/ rd the pin function is switched as shown below according to the combination of the p95ddr bit and the expe bit in mdcr. expe 0 1 p95ddr 0 1 ? pin function p95 input p95 output rd output ? p94/ hwr the pin function is switched as shown below acc ording to the combination of the p94ddr bit and the expe bit in mdcr. expe 0 1 p94ddr 0 1 ? pin function p94 input p94 output hwr output
rev. 2.00, 03/04, page 257 of 534 ? p93/ lwr the pin function is switched as shown below according to the combination of the p93ddr bit and the expe bit in mdcr. expe 0 1 bus mode ? all areas are 8-bit space at least one area is 16-bit space p93ddr 0 1 0 1 ? pin function p93 input p93 output p93 input p93 output lwr output ? p92/ cs2 / ras the pin function is switched as shown below according to the combination of the p92ddr bit, the expe bit in mdcr, and the cs2e bit in pfcr1. expe 0 1 area 2 ? normal space dram space cs2e ? 0 1 ? p92ddr 0 1 0 1 ? ? pin function p92 input p92 output p92 input p92 output cs2 output ras output ? p91/ cs1 the pin function is switched as shown below according to the combination of the p91ddr bit, the expe bit in mdcr, and the cs1e bit in pfcr1. expe 0 1 cs1e ? 0 1 p91ddr 0 1 0 1 ? pin function p91 input p91 output p91 input p91 output cs1 output ? p90/ cs0 the pin function is switched as shown below according to the combination of the p90ddr bit and the expe bit in mdcr. expe 0 1 p90ddr 0 1 ? pin function p90 input p90 output cs0 output
rev. 2.00, 03/04, page 258 of 534 8.10 port a port a is a 4-bit i/o port that also has other functions. the port a has the following registers. ? port a data direction register (paddr) ? port a data register (padr) ? port a register (porta) 8.10.1 port a data di rection register (paddr) the individual bits of paddr specify input or output for the pins of port a. paddr cannot be read; if it is, an undefined value will be read. bit bit name initial value r/w description 7 to 4 ? undefined ? reserved if these bits are read, an undefined value will be read. these bits cannot be modified. 3 2 1 0 pa3ddr pa2ddr pa1ddr pa0ddr 0 0 0 0 w w w w when a pin function is specified to a general purpose i/o, setting this bit to 1 ma kes the corresponding port a pin an output pin, while clearing this bit to 0 makes the pin an input pin. 8.10.2 port a data register (padr) padr stores output data for the port a pins. bit bit name initial value r/w description 7 to 4 ? undefined ? reserved if these bits are read, an undefined value will be read. these bits cannot be modified. 3 2 1 0 pa3dr pa2dr pa1dr pa0dr 0 0 0 0 r/w r/w r/w r/w output data for a pin is stored when the pin function is specified to a general purpose output.
rev. 2.00, 03/04, page 259 of 534 8.10.3 port a register (porta) porta shows the pin states of the port a. porta cannot be modified. bit bit name initial value r/w description 7 rxdmon ? * 1 r this bit is read as the reversed value of the hudidi/rxd0 pin. 1 is read when the hudidi/rxd0 pin is low, and 0 is read when hudidi/rxd0 pin is high. 6 to 4 ? undefined ? reserved if these bits are read, an undefined value will be read. 3 2 1 0 pa3 pa2 pa1 pa0 ? * 2 ? * 2 ? * 2 ? * 2 r r r r if a porta read is performed while paddr bits are set to 1, the padr values are read. if a porta read is performed while paddr bits are cleared to 0, the pin states are read. notes: 1. determined by the state of the hudidi/rxd0 pin. 2. determined by the states of pins pa3 to pa0. 8.10.4 pin functions port a pins also function as the pins for external address bus output, external bus control signal output, and interrupt input. the correspondence between the register specification and the pin functions is shown below. ? pa3/a19/ cs3 the pin function is switched as shown below according to the combination of the pa3ddr bit, the expe bit in mdcr, and the cs3e and ahoe bits in pfcr1. expe 0 1 cs3e ? 0 1 ahoe ? 0 1 ? pa3ddr 0 1 0 1 ? ? pin function pa3 input pa3 output pa3 input pa3 output a19 output cs3 output
rev. 2.00, 03/04, page 260 of 534 ? pa2/a18/ ucas the pin function is switched as shown below according to the combin ation of the pa2ddr bit, the expe bit in mdcr, and the ahoe bit in pfcr1. expe 0 1 area 2 ? normal space dram space ahoe ? 0 1 ? pa2ddr 0 1 0 1 ? ? pin function pa2 input pa2 output pa2 input pa2 output a18 output ucas output ? pa1/a18/ ucas the pin function is switched as shown below according to the combin ation of the pa2ddr bit, the expe bit in mdcr, and the ahoe bit in pfcr1. expe 0 1 area 2 ? normal space dram space ahoe ? 0 1 ? pa1ddr 0 1 0 1 ? ? pa1 input pa1 output pa1 input pa1 output a17 output lcas output pin function irq1 interrupt input * note: * when iss1 = 1, this pin functions as irq1 interrupt input. ? pa0/a16/( irq0 ) the pin function is switched as shown below according to the combin ation of the pa0ddr bit, the expe bit in mdcr, the ahoe bit in pfcr1, and the iss0 bit in issr. expe 0 1 ahoe ? 0 1 pa0ddr 0 1 0 1 ? pa0 input pa0 output pa0 input pa0 output a16 output pin function irq0 interrupt input * note: * when iss0 = 1, this pin functions as irq0 interrupt input.
rev. 2.00, 03/04, page 261 of 534 8.11 pin selection 8.11.1 port function control register 1 (pfcr1) pfcr1 performs i/o port control for the external interface pin and output pin. bit bit name initial value r/w description 7 ? 0 r/w reserved this bit can be read from or written to. however, the write value should always be 0. 6 cs1e 0 r/w cs1 enable enables or disables output for cs1 . 0: set as i/o port 1: set as cs1 output pin 5 cs2e 0 r/w cs2 enable enables or disables output for cs2 . 0: set as i/o port 1: set as cs2 output pin 4 cs3e 0 r/w cs3 enable enables or disables output for cs3 . 0: set as i/o port 1: set as cs3 output pin 3 ckoe 1 r/w output enable enables or disables output for . 0: set as i/o port 1: set as output pin 2 aloe 1 r/w address output enable enables or disables address output. 0: set as i/o port 1: set a7 to a0 pins as address output pins 1 amoe 1 r/w address output enable enables or disables address output. 0: set as i/o port 1: set a15 to a8 pins as address output pins
rev. 2.00, 03/04, page 262 of 534 bit bit name initial value r/w description 0 ahoe 0 r/w address output enable enables or disables address output. 0: set as i/o port 1: set a19 to a16 pins as address output pins 8.11.2 irq sense port select register (issr) issr selects the input pins for irq7 to irq0. bit bit name initial value r/w description 7 iss7 0 r/w selects an input pin for irq7 . 0: p77 1: p57 6 iss6 0 r/w selects an input pin for irq6 . 0: p76 1: p56 5 iss5 0 r/w selects an input pin for irq5 . 0: p75 1: p35 4 iss4 0 r/w selects an input pin for irq4 . 0: p74 1: p34 3 iss3 0 r/w selects an input pin for irq3 . 0: p73 1: p53 2 iss2 0 r/w selects an input pin for irq2 . 0: p72 1: p52 1 iss1 0 r/w selects an input pin for irq1 . 0: p71 1: pa1 0 iss0 0 r/w selects an input pin for irq0 . 0: p70 1: pa0
rev. 2.00, 03/04, page 263 of 534 section 9 8-bit timer (tmr) this lsi has an on-chip 8-bit timer module with two channels operating on the basis of an 8-bit counter. the 8-bit timer module can be used to count external events and be used as a multifunction timer in a variety of applications, such as generation of counter reset, interrupt requests, and pulse output with an arbitrary duty cycle using a compare-match signal with two registers. 9.1 features ? selection of four clock sources the counters can be driven by one of three internal clock signals ( /8, /64, or /8192) or an external clock input ? selection of three ways to clear the counters the counters can be cleared on compare match a or b, or by an external reset signal ? timer output control by a combination of two compare match signals the timer output signal in each channel is controlled by a combination of two independent compare match signals, enabling the timer to generate output waveforms with an arbitrary duty cycle or pwm output ? provision for cascading of two channels (tmr_0 and tmr_1) operation as a 16-bit timer is possible, using tmr_0 for the upper 8 bits and tmr_1 for the lower 8 bits (16-bit count mode) tmr_1 can be used to count tmr_0 compare matches (compare match count mode) ? three independent interrupts compare match a and b and overflow interrupts can be requested independently
rev. 2.00, 03/04, page 264 of 534 figure 9.1 shows a block diagram of the 8-bit timer module (tmr_0 and tmr_1). external clock source internal clock sources tmr_0 /8 /64 /8192 tmr_1 /8 /64 /8192 clock 1 clock 0 compare match a1 compare match a0 clear 1 cmia0 cmib0 ovi0 cmia1 cmib1 ovi1 interrupt signals tcora_0 : time constant register a_0 tcorb_0 : time constant register b_0 tcnt_0 : timer counter_0 tcsr_0 : timer control/status register_0 tcr_0 : timer control register_0 tcora_1 : time constant register a_1 tcorb_1 : time constant register b_1 tcnt_1 : timer counter_1 tcsr_1 : timer control/status register_1 tcr_1 : timer control register_1 tmo0 tmri0 internal bus tcora_0 comparator a_0 comparator b_0 tcorb_0 tcsr_0 tcr_0 tcora_1 comparator a_1 tcnt_1 comparator b_1 tcorb_1 tcsr_1 tcr_1 tmci0 tmci1 tcnt_0 overflow 1 overflow 0 compare match b1 compare match b0 tmo1 tmri1 clock select control logic clear 0 [legend] figure 9.1 block diagram of 8-bit timer module
rev. 2.00, 03/04, page 265 of 534 9.2 input/output pins table 9.1 shows the pin configuration of the 8-bit timer module. table 9.1 pin configuration channel name sy mbol i/o function 0 timer output pin tmo0 output outputs at compare match timer clock input pin tmci0 input inputs external clock for counter timer reset input pin tmri0 input inputs external reset to counter 1 timer output pin tmo1 output outputs at compare match timer clock input pin tmci1 input inputs external clock for counter timer reset input pin tmri1 input inputs external reset to counter 9.3 register descriptions the 8-bit timer module has the following registers. for details on the module stop control register, refer to section 16.1.2 module stop control registers h and l (mstpcrh, mstpcrl). ? timer counter_0 (tcnt_0) ? time constant register a_0 (tcora_0) ? time constant register b_0 (tcorb_0) ? timer control register_0 (tcr_0) ? timer control/status register_0 (tcsr_0) ? timer counter_1 (tcnt_1) ? time constant register a_1 (tcora_1) ? time constant register b_1 (tcorb_1) ? timer control register_1 (tcr_1) ? timer control/status register_1 (tcsr_1) 9.3.1 timer counter (tcnt) tcnt is 8-bit up-counter. tcnt_0 and tcnt_1 comprise a single 16-bit register so they can be accessed together by a word transfer instruction. bits cks2 to cks0 in tcr are used to select a clock. tcnt can be cleared by an external rese t input or by a compare match signal a or b. which signal is to be used for clearing is selected by bits cclr1 and cclr0 in tcr. when tcnt overflows from h'ff to h'00, ovf in tcsr is set to 1. tcnt is initialized to h'00.
rev. 2.00, 03/04, page 266 of 534 9.3.2 time constant register a (tcora) tcora is 8-bit readable/writable register. tcora_0 and tcora_1 comprise a single 16-bit register so they can be accessed togeth er by a word tran sfer instruction. the value in tcora is continually compared with the value in tcnt. when a match is detected, the corresponding cmfa flag in tcsr is set to 1. note, however, that comparison is disabled during the t2 state of a tcora write cycle. the timer output from the tmo pin can be freely controlled by this compare match signal (compare match a) and the settings of bits os1 and os0 in tcsr. tcora is initialized to h'ff. 9.3.3 time constant register b (tcorb) tcorb is 8-bit readable/writable register. tcorb_0 and tcorb_1 comprise a single 16-bit register so they can be accessed togeth er by a word tran sfer instruction. tcorb is continually compared with the value in tcnt. when a match is detected, the corresponding cmfb flag in tcsr is set to 1. note, however, that comparison is disabled during the t2 state of a tcobr write cycle. the timer output from the tmo pin can be freely controlled by this compare match signal (compare match b) and the settings of bits os3 and os2 in tcsr. tcorb is initialized to h'ff. 9.3.4 timer control register (tcr) tcr selects the clock source and the time at which tcnt is cleared, and controls interrupts. bit bit name initial value r/w description 7 cmieb 0 r/w compare match interrupt enable b selects whether cmfb interrupt requests (cmib) are enabled or disabled when the cmfb flag in tcsr is set to 1. 0: cmfb interrupt requests (cmib) are disabled 1: cmfb interrupt requests (cmib) are enabled
rev. 2.00, 03/04, page 267 of 534 bit bit name initial value r/w description 6 cmiea 0 r/w compare match interrupt enable a selects whether cmfa interrupt requests (cmia) are enabled or disabled when the cmfa flag in tcsr is set to 1. 0: cmfa interrupt requests (cmia) are disabled 1: cmfa interrupt requests (cmia) are enabled 5 ovie 0 r/w timer overflow interrupt enable selects whether ovf interrupt requests (ovi) are enabled or disabled when the ovf flag in tcsr is set to 1. 0: ovf interrupt requests (ovi) are disabled 1: ovf interrupt requests (ovi) are enabled 4 3 cclr1 cclr0 0 0 r/w r/w counter clear 1 and 0 these bits select the method by which tcnt is cleared 00: clearing is disabled 01: clear by compare match a 10: clear by compare match b 11: clear by rising edge of external reset input 2 1 0 cks2 cks1 cks0 0 0 0 r/w r/w r/w clock select 2 to 0 these bits select the clock input to tcnt and count condition. see table 9.2.
rev. 2.00, 03/04, page 268 of 534 table 9.2 clock input to tcnt and count condition tcr channel bit 2 cks2 bit 1 cks1 bit 0 cks0 description tmr_0 0 0 0 clock input disabled 1 internal clock, counted at falling edge of /8 1 0 internal clock, counted at falling edge of /64 1 internal clock, counted at falling edge of /8192 1 0 0 count at tcnt_1 overflow signal * tmr_1 0 0 0 clock input disabled 1 internal clock, counted at falling edge of /8 1 0 internal clock, counted at falling edge of /64 1 internal clock, counted at falling edge of /8192 1 0 0 count at tcnt_0 compare match a * all 1 0 1 external clock, counted at rising edge 1 0 external clock, counted at falling edge 1 1 external clock, counted at both rising and falling edges note: if the count input of tmr_0 is the tcnt_1 overflow signal and that of tmr_1 is the tcnt_0 compare match signal, no incrementing cl ock is generated. do not use this setting. 9.3.5 timer control/status register (tcsr) tcsr displays status flags, and controls compare match output. bit bit name initial value r/w description 7 cmfb 0 r/(w) * compare match flag b [setting condition] ? set when tcnt matches tcorb [clearing condition] ? cleared by reading cmfb when cmfb = 1, then writing 0 to cmfb
rev. 2.00, 03/04, page 269 of 534 bit bit name initial value r/w description 6 cmfa 0 r/(w) * compare match flag a [setting condition] ? set when tcnt matches tcora [clearing condition] ? cleared by reading cmfa when cmfa = 1, then writing 0 to cmfa 5 ovf 0 r/(w) * timer overflow flag [setting condition] ? set when tcnt overflows from h'ff to h'00 [clearing condition] ? cleared by reading ovf when ovf = 1, then writing 0 to ovf 4 ? undefined ? reserved this bit is always read as an undefined value, and cannot be modified. 3 2 os3 os2 0 0 r/w r/w output select 3 and 2 these bits select a method of tmo pin output when compare match b of tcorb and tcnt occurs. 00: no change when compare match b occurs 01: 0 is output when compare match b occurs 10: 1 is output when compare match b occurs 11: output is inverted when compare match b occurs (toggle output) 1 0 os1 os0 0 0 r/w r/w output select 1 and 0 these bits select a method of tmo pin output when compare match a of tcora and tcnt occurs. 00: no change when compare match a occurs 01: 0 is output when compare match a occurs 10: 1 is output when compare match a occurs 11: output is inverted when compare match a occurs (toggle output) note: only 0 can be written to clear these flags.
rev. 2.00, 03/04, page 270 of 534 9.4 operation 9.4.1 pulse output figure 9.2 shows an example that the 8-bit timer is used to generate a pulse output with a selected duty cycle. the control bits are set as follows: 1 in tcr, bit cclr1 is cleared to 0 and bit cclr0 is set to 1 so that the timer counter is cleared at a tcora compare match. 2 in tcsr, bits os3 to os0 are set to b'0110, causing the output to change to 1 at a tcora compare match and to 0 at a tcorb compare match. with these settings, the 8-bit timer provides output of pulses at a rate determined by tcora with a pulse width determined by tcorb. no software intervention is required. tcnt h'ff counter clear tcora tcorb h'00 tmo figure 9.2 example of pulse output
rev. 2.00, 03/04, page 271 of 534 9.5 operation timing 9.5.1 tcnt incrementation timing figure 9.3 shows the count timing for internal clock input. figure 9.4 shows the count timing for external clock signal. note that the external clock pulse width mu st be at least 1.5 states for incrementation at a single edge, and at least 2. 5 states for incrementation at both edges. the counter will not increment correctly if th e pulse width is less than these values. internal clock clock input to tcnt tcnt n?1 n n+1 figure 9.3 count timing for internal clock input external clock input pin clock input to tcnt tcnt n?1 n n+1 figure 9.4 count timing for external clock input
rev. 2.00, 03/04, page 272 of 534 9.5.2 timing of cmfa and cmfb setting when compare-match occurs the cmfa and cmfb flags in tcsr are set to 1 by a compare match signal generated when the tcor and tcnt values match. the compare match signal is generated at the last state in which the match is true, just before the timer counter is updated. therefore, when tcor and tcnt match, the compare match signal is not generated until the next incrementation clock input. figure 9.5 shows this timing. tcnt n n+1 tcor n compare match signal cmf figure 9.5 timing of cmf setting 9.5.3 timing of timer output when compare-match occurs when compare match a or b occurs, the timer output changes as specified by bits os3 to os0 in tcsr. figure 9.6 shows the timing when the output is set to toggle at compare match a. compare match a signal timer output pin figure 9.6 timing of timer output
rev. 2.00, 03/04, page 273 of 534 9.5.4 timing of compare match clear tcnt is cleared when compare match a or b occurs, depending on the setting of the cclr1 and cclr0 bits in tcr. figure 9.7 shows the timing of this operation. n h'00 compare match signal tcnt figure 9.7 timing of compare match clear 9.5.5 timing of tcnt external reset tcnt is cleared at the rising edge of an external reset input, depending on the settings of the cclr1 and cclr0 bits in tcr. the clear pulse width must be at least 1.5 states. figure 9.8 shows the timing of this operation. clear signal external reset input pin tcnt n h'00 n?1 figure 9.8 timing of clearance by external reset 9.5.6 timing of overflow flag (ovf) setting the ovf in tcsr is set to 1 when tcnt overflows (changes from h'ff to h'00). figure 9.9 shows the timing of this operation.
rev. 2.00, 03/04, page 274 of 534 ovf overflow signal tcnt h'ff h'00 figure 9.9 timing of ovf setting 9.6 operation with cascaded connection if bits cks2 to cks0 in either tcr_0 or tcr_1 are set to b'100, the 8-bit timers of the two channels are cascaded. with this configuration, a single 16-bit timer could be used (16-bit counter mode) or compare matches of the 8-bit channel 0 could be counted by the timer of channel 1 (compare match count mode). in this case, the timer operates as below. 9.6.1 16-bit counter mode when bits cks2 to cks0 in tcr_0 are set to b' 100, the timer functions as a single 16-bit timer with channel 0 occupying the upper 8 bits and channel 1 occupying the lower 8 bits. 1 setting of compare match flags ? the cmf flag in tcsr_0 is set to 1 when a 16-bit compare match event occurs. ? the cmf flag in tcsr_1 is set to 1 when a lower 8-bit compare match event occurs. 2 counter clear specification ? if the cclr1 and cclr0 bits in tcr_0 have been set for counter clear at compare match, the 16-bit counters (tcnt_0 and tcnt_1 together ) are cleared when a 16-bit compare match event occurs. the 16-bit counters (tcnt0 and tc nt1 together) are cleared even if counter clear by the tmri0 pin has also been set. ? the settings of the cclr1 and cclr0 bits in tc r_1 are ignored. the lower 8 bits cannot be cleared independently. 3 pin output ? control of output from the tmo0 pin by bits os3 to os0 in tcsr_0 is in accordance with the 16-bit compare match conditions. ? control of output from the tmo1 pin by bits os3 to os0 in tcsr_1 is in accordance with the lower 8-bit compare match conditions.
rev. 2.00, 03/04, page 275 of 534 9.6.2 compare match count mode when bits cks2 to cks0 in tcr_1 are b'100, tcnt_1 counts compare match a's for channel 0. channels 0 and 1 are controlled independently. conditions such as setting of the cmf flag, generation of interrupts, output from the tmo pin, and counter clear are in accordance with the settings for each channel. 9.7 interrupt sources 9.7.1 interrupt sources there are three 8-bit timer interrupt sources: cm ia, cmib, and ovi. their relative priorities are shown in table 9.3. each interrupt source is se t as enabled or disabled by the corresponding interrupt enable bit in tcr or tcsr, and independent interrupt requests are sent for each to the interrupt controller. table 9.3 8-bit timer interrupt sources name interrupt source interrupt flag priority cmia0 tcora_0 compare match cmfa high cmib0 tcorb_0 compare match cmfb ovi0 tcnt_0 overflow ovf low cmia1 tcora_1 compare match cmfa high cmib1 tcorb_1 compare match cmfb ovi1 tcnt_1 overflow ovf low
rev. 2.00, 03/04, page 276 of 534 9.8 usage notes 9.8.1 contention between tcnt write and clear if a timer counter clock pulse is generated during the t 2 state of a tcnt write cycle, the clear takes priority, so that the counter is cleared and the write is not performed. figure 9.10 shows this operation. address tcnt address internal write signal counter clear signal tcnt n h'00 t 1 t 2 tcnt write cycle by cpu figure 9.10 contention between tcnt write and clear
rev. 2.00, 03/04, page 277 of 534 9.8.2 contention between tcnt write and increment if a timer counter clock pulse is generated during the t 2 state of a tcnt write cycle, the write takes priority and the counter is not incremented. figure 9.11 shows this operation. address tcnt address internal write signal tcnt input clock tcnt nm t 1 t 2 tcnt write cycle by cpu counter write data figure 9.11 contention between tcnt write and increment
rev. 2.00, 03/04, page 278 of 534 9.8.3 contention between tcor write and compare match during the t 2 state of a tcor write cycle, the tcor write has priority and the compare match signal is inhibited even if a compare match event occurs as shown in figure 9.12. in tmr, an icr imput capture conflicts with a co mpare match in the same way as with a write to tcor. in this case also, imput capture has prio rity and the compare match signal is inhibited. address tcor address internal write signal tcnt tcor nm t 1 t 2 tcor write cycle by cpu tcor write data n n+1 compare match signal inhibited figure 9.12 contention between tcor write and compare match
rev. 2.00, 03/04, page 279 of 534 9.8.4 contention between compare matches a and b if compare match events a and b occur at the same time, the 8-bit timer operates in accordance with the priorities for the output statuses set fo r compare match a and comp are match b, as shown in table 9.4. table 9.4 timer output priorities output setting priority toggle output high 1 output 0 output no change low 9.8.5 switching of internal clocks and tcnt operation tcnt may increment erroneously when the internal clock is switched over. table 9.5 shows the relationship between the timing at which the internal clock is switched (by writing to the cks1 and cks0 bits) and the tcnt operation. when the tcnt clock is generated from an internal clock, the falling edge of the internal clock pulse is detected. if clock switching causes a change from high to low level, as shown in case 3 in table 9.5, a tcnt clock pulse is generated on the assumption that the switchover is a falling edge. this increments tcnt. the erroneous incrementation can also happen wh en switching between internal and external clocks.
rev. 2.00, 03/04, page 280 of 534 table 9.5 switching of internal clock and tcnt operation no. timing of switchover by means of cks1 and cks0 bits tcnt clock operation 1 switching from low to low * 1 clock before switchover clock after switchover tcnt clock tcnt cks bit write n n + 1 2 switching from low to high * 2 clock before switchover clock after switchover tcnt clock tcnt cks bit write n n + 1 n + 2 3 switching from high to low * 3 clock before switchover clock after switchover tcnt clock tcnt cks bit write n n + 1 n + 2 * 4
rev. 2.00, 03/04, page 281 of 534 no. timing of switchover by means of cks1 and cks0 bits tcnt clock operation 4 switching from high to high clock before switchover clock after switchover tcnt clock tcnt cks bit write n n + 1 n + 2 notes: 1. includes switching from low to stop, and from stop to low. 2. includes switching from stop to high. 3. includes switching from high to stop. 4. generated on the assump tion that the switchover is a falling edge; tcnt is incremented. 9.8.6 mode setting with cascaded connection if 16-bit counter mode and compare match count mode are specified at the same time, input clocks for tcnt_0 and tcnt_1 are not generated, and the counter stops. do not specify 16-bit counter and compare match count modes simultaneously. 9.8.7 interrupts in module stop mode if module stop mode is entered when an interrupt has been requested, it will not be possible to clear the cpu interrupt source. interrupts should th erefore be disabled before entering module stop mode.
rev. 2.00, 03/04, page 282 of 534
rev. 2.00, 03/04, page 283 of 534 section 10 watchdog timer (wdt) this lsi incorporates an 8-bit watchdog timer with one channel (wdt). if a system crash prevents the cpu from writing to the timer counter, thus allowing it to overflow, the wdt can generate an internal reset signal or an internal nmi interrupt signal. when this watchdog function is not needed, the wdt can be used as an interval timer. in interval timer operation, an interval timer interrupt is generated each time the counter overflows. a block diagram of the wdt is shown in figure 10.1. 10.1 features ? selectable from eight counter input clocks. ? switchable between watchdog timer mode and interval timer mode watchdog timer mode: ? if the counter overflows, an internal reset or an internal nmi interrupt is generated. internal timer mode: ? if the counter overflows, an internal timer interrupt (wovi) is generated. wovi (interrupt request signal) internal nmi (interrupt request signal) internal reset signal tcnt tcsr /2 /64 /128 /512 /2048 /8192 /32768 /131072 internal clock tcsr : timer control/status register tcnt : timer counter legend overflow interrupt control reset control clock clock selection bus interface module bus internal bus wdt figure 10.1 block diagram of wdt
rev. 2.00, 03/04, page 284 of 534 10.2 register descriptions the wdt has the following regist ers. to prevent accidental overw riting, tcsr and tcnt have to be written to in a method different from norma l registers. for details, see section 10.5.1, notes on register access. ? timer counter (tcnt) ? timer control/status register (tcsr) 10.2.1 timer counter (tcnt) tcnt is an 8-bit readable/writable up-counter. tc nt is initialized to h'00 when the tme bit in timer control/status register (tcsr) is cleared to 0. 10.2.2 timer control/s tatus register (tcsr) tcsr selects the clock source to be input to tcnt, and the timer mode. bit bit name initial value r/w description 7 ovf 0 r/(w) * 1 overflow flag indicates that tcnt has overflowed (changes from h'ff to h'00). [setting condition] when tcnt overflows (changes from h'ff to h'00) when internal reset request generation is selected in watchdog timer mode, ovf is cleared automatically by the internal reset. [clearing conditions] ? when tcsr is read when ovf = 1 * 2 , then 0 is written to ovf ? when 0 is written to tme 6 wt/ it 0 r/w timer mode select selects whether the wdt is used as a watchdog timer or interval timer. 0: interval timer mode 1: watchdog timer mode
rev. 2.00, 03/04, page 285 of 534 bit bit name initial value r/w description 5 tme 0 r/w timer enable when this bit is set to 1, tcnt starts counting. when this bit is cleared, tcnt stops counting and is initialized to h'00. 4 ? 0 r/w reserved the initial value should not be changed. 3 rst/ nmi 0 r/w reset or nmi selects to request an internal reset or an nmi interrupt when tcnt has overflowed. 0: an nmi interrupt is requested 1: an internal reset is requested 2 1 0 cks2 cks1 cks0 0 0 0 r/w r/w r/w clock select 2 to 0 selects the clock source to be input to. the overflow frequency for = 33 mhz is enclosed in parentheses. 000: /2 (frequency: 15.5 s) 001: /64 (frequency: 496.4 s) 010: /128 (frequency: 992.9 s) 011: /512 (frequency: 3.9 ms) 100: /2048 (frequency: 15.8 ms) 101: /8192 (frequency: 63.5 ms) 110: /32768 (frequency: 254.2 ms) 111: /131072 (frequency: 1.01 s) notes: 1. only 0 can be wr itten to clear the flag. 2. when the ovf flag is polled with the interv al timer interrupt disabled, ovf = 1 must be read at least twice.
rev. 2.00, 03/04, page 286 of 534 10.3 operation 10.3.1 watchdog timer mode to use the wdt as a watchdog timer, set the wt/ it bit and the tme bit in tcsr to 1. while the wdt is used as a watchdog timer, if tcnt overflows without being rewritten because of a system malfunction or another error, an internal reset or nmi interrupt request is generated. tcnt does not overflow while the sy stem is operating normally. software must prevent tcnt overflows by rewriting the tcnt value (normally be writing h'00) before overflows occurs. if the rst/ nmi bit of tcsr is set to 1, when the tcnt overflows, an internal reset signal for this lsi is issued for 518 system clocks as shown in figure 10.2. if the rst/ nmi bit is cleared to 0, when the tcnt overflows, an nmi interrupt request is generated. an internal reset request from the watchdog timer and a reset input from the res pin are processed in the same vector. reset source can be identified by the xrst bit status in syscr. if a reset caused by a signal input to the res pin occurs at the same time as a reset caused by a wdt overflow, the res pin reset has priority and the xrst bit in syscr is set to 1. an nmi interrupt request from the watchdog timer and an interrupt request from the nmi pin are processed in the same vector. do not handle an nmi interrupt request from the watchdog timer and an interrupt request from the nmi pin at the same time. tcnt value h'00 time h'ff wt/ it = 1 tme = 1 write h'00 to tcnt wt/ it = 1 tme = 1 write h'00 to tcnt 518 system clocks internal reset signal wt/ it : tme : ovf : overflow ovf = 1 * timer mode select bit timer enable bit overflow flag note * after the ovf bit becomes 1, it is cleared to 0 by an internal reset. the xrst bit is also cleared to 0. figure 10.2 watchdog timer mode (rst/ nmi = 1) operation
rev. 2.00, 03/04, page 287 of 534 10.3.2 interval timer mode when the wdt is used as an interval timer, an interval timer interrupt (wovi) is generated each time the tcnt overflows, as shown in figure 10.3 . therefore, an interrupt can be generated at intervals. when the tcnt overflows in interval timer mode, an interval timer interrupt (wovi) is requested at the same time the ovf bit of tcsr is set to 1. the timing is shown figure 10.4. tcnt value h'00 time h'ff wt/ = 0 tme = 1 wovi overflow overflow overflow overflow wovi : internal timer interrupt request occurrence wovi wovi wovi figure 10.3 interval timer mode operation tcnt h'ff h'00 overflow signal (internal signal) ovf figure 10.4 ovf flag set timing
rev. 2.00, 03/04, page 288 of 534 10.3.3 watchdog timer ov erflow flag (ovf) timing when tcnt overflows in watchdog timer mode, the ovf bit in tcsr is set to 1. when the rst/ nmi bit is 1 here, the internal reset signal is generated for the entire lsi. the timing is shown in figure 10.5. tcnt h'ff h'00 518 states overflow signal (internal signal) ovf internal reset signal figure 10.5 output timing of ovf 10.4 interrupt sources during interval timer mode operation, an overflow generates an interval timer interrupt (wovi). the interval timer interrupt is requested whenever the ovf flag is set to 1 in tcsr. ovf must be cleared to 0 in the interrupt handling routine. when the nmi interrupt request is selected in watchdog timer mode, an nmi interrupt request is generated by an overflow. table 10.1 wdt interrupt source name interrupt source interrupt flag wovi tcnt overflow ovf
rev. 2.00, 03/04, page 289 of 534 10.5 usage notes 10.5.1 notes on register access the watchdog timer's registers, tcnt and tcsr differ from other registers in being more difficult to write to. the procedures for writing to and reading from these registers are given below. writing to tcnt and tcsr: these registers must be written to by a word transf er instruction. they cannot be written to by a byte transfer instruction. tcnt and tcsr both have the same write addr ess. therefore, satisf y the relative condition shown in figure 10.6 to write to tcnt or tcsr. to write to tcnt, the higher bytes must contain the value h'5a and the lower bytes must contain the write data before the transfer instruction execution. to write to tcsr, the higher bytes must contain the value h'a5 and the lower bytes must contain the write data. address : h'fe70 address : h'fe70 h'5a write data 15 8 7 0 0 h'a5 write data 15 8 7 0 0 figure 10.6 writing to tcnt and tcsr reading from tcnt and tcsr: these registers are read in the same way as other registers. the read addr ess is h'fe70 for tcsr and h'fe71 for tcnt.
rev. 2.00, 03/04, page 290 of 534 10.5.2 conflict between timer co unter (tcnt) write and increment if a timer counter clock pulse is generated during the t2 state of a tcnt write cycle, the write takes priority and the timer counter is not incremented. figure 10.7 shows this operation. address internal write signal tcnt input clock tcnt nm t 1 t 2 tcnt write cycle counter write data figure 10.7 conflict between tcnt write and increment 10.5.3 changing values of cks2 to cks0 bits if bits cks2 to cks0 in tcsr are written to wh ile the wdt is operating, errors could occur in the incrementation. software must stop the watchdog timer (by clearing the tme bit to 0) before changing the values of bits cks2 to cks0. 10.5.4 switching between watchdog ti mer mode and interval timer mode if the mode is switched from watchdog timer to interval timer, while the wdt is operating, errors could occur in the incrementation. software must stop the watchdog timer (by clearing the tme bit to 0) before switching the mode.
rev. 2.00, 03/04, page 291 of 534 section 11 serial communica tion interface for boot mode (sci) this lsi has a serial communication interfac e for boot mode (sci) which is on-board programming mode of flash memory. the sci can handle asynchronous serial communication. serial data communication can be carried out wi th standard asynchrono us communication chips such as a universal asynchronous recei ver/transmitter (uart) or asynchronous communication interface adapter (acia). figure 11.1 shows a block diagram of the sci. 11.1 features ? choice of asynchronous or clocked synchronous serial communication mode ? full-duplex communication capability the transmitter and receiver are mutually independ ent, enabling transmission and reception to be executed simultaneously. double-buffering is used in both the transmitter and the receiver, enabling continuous transmission and continuous reception of serial data. ? on-chip baud rate generator allows any bit rate to be selected ? choice of lsb-first ? four interrupt sources four interrupt sources ? transmit-end, transmit-data-empty , receive-data-full, and receive error ? that can issue requests. ? module stop mode can be set asynchronous mode ? data length: 7 or 8 bits ? stop bit length: 1 or 2 bits ? parity: even, odd, or none ? receive error detection: parity , overrun, and framing errors ? break detection: break can be detected by r eading the rxd pin level directly in case of a framing error
rev. 2.00, 03/04, page 292 of 534 rxd txd clock /4 /16 /64 tei txi rxi eri ssr scr smr transmission/ reception control baud rate generator brr module data bus rdr tsr rsr parity generation parity check tdr bus interface internal data bus [legend] rsr : receive shift register rdr : receive data register tsr : transmit shift register tdr : transmit data register smr : serial mode register scr : serial control register ssr : serial status register brr : bit rate register figure 11.1 block diagram of sci 11.2 input/output pins table 11.1 shows the pin configuration of the sci. table 11.1 pin configuration channel pin name * i/o function rxd0 input channel 0 receive data input 0 txd0 output channel 0 transmit data output note: * pin names rxd and txd are used in the text, omitting the channel designation.
rev. 2.00, 03/04, page 293 of 534 11.3 register descriptions the sci has the following registers. for details on the module stop contro l register, see section 16.1.2, module stop control registers h and l (mstpcrh, mstpcrl). to read the state of the rxd pin, see section 8.10.3, port a register (porta). ? receive shift register (rsr) ? transmit shift register (tsr) ? receive data register (rdr) ? transmit data register (tdr) ? serial mode register (smr) ? serial control register (scr) ? serial status register (ssr) ? bit rate register (brr) 11.3.1 receive shi ft register (rsr) rsr is a shift register used to receive serial data that is input to the rxd pin and convert it into parallel data. when one byte of data has been received, it is transferre d to rdr automatically. rsr cannot be directly accessed by the cpu. 11.3.2 receive data register (rdr) rdr is an 8-bit register that stores receive da ta. when the sci has received one byte of serial data, it transfers the received serial data from rs r to rdr where it is stored. after this, rsr is receive-enabled. since rsr and rdr function as a double buffer in this wa y, enables continuous receive operations to be performed. after confirmi ng that the rdrf bit in ssr is set to 1, read rdr for only once. rdr cannot be written to by the cpu. 11.3.3 transmit data register (tdr) tdr is an 8-bit register that stores transmit data. when the sci detects that tsr is empty, it transfers the transmit data written in tdr to ts r and starts transmission. the double-buffered structures of tdr and tsr enable continuous seri al transmission. if the next transmit data has already been written to tdr during serial transmi ssion, the sci transfers the written data to tsr to continue transmission. although tdr can be read or written to by the cpu at all times, to achieve reliable serial transmission, write transmit data to tdr for only once after confirming that the tdre bit in ssr is set to 1.
rev. 2.00, 03/04, page 294 of 534 11.3.4 transmit shift register (tsr) tsr is a shift register that transmits serial data. to perform serial data transmission, the sci first transfers transmit data fr om tdr to tsr, then sends the data to the txd pin starting. tsr cannot be directly accessed by the cpu. 11.3.5 serial mode register (smr) smr is used to set the sci's serial transfer format and select the on-chip baud rate generator clock source. bit bit name initial value r/w description 7 c/ a 0 r/w communication mode 0: asynchronous mode 1: setting prohibited 6 chr 0 r/w character length (enabled only in asynchronous mode) 0: selects 8 bits as the data length. 1: selects 7 bits as the data length. the msb (bit 7) of tdr is not transmitted in transmission. 5 pe 0 r/w parity enable (enabled only in asynchronous mode) when this bit is set to 1, the parity bit is added to transmit data before transmission, and the parity bit is checked in reception. 4 o/ e 0 r/w parity mode (enabled only when the pe bit is 1 in asynchronous mode) 0: selects even parity. 1: selects odd parity. 3 stop 0 r/w stop bit length (enabled only in asynchronous mode) selects the stop bit length in transmission. 0: 1 stop bit 1: 2 stop bits in reception, only the first stop bit is checked regardless of the stop bit setting. if the second stop bit is 0, it is treated as the start bit of the next transmit character. 2 ? 0 r/w reserved the initial value should not be changed.
rev. 2.00, 03/04, page 295 of 534 bit bit name initial value r/w description 1 0 cks1 cks0 0 0 r/w r/w clock select 1 and 0 these bits select the clock source for the on-chip baud rate generator. 00: clock (n = 0) 01: /4 clock (n = 1) 10: /16 clock (n = 2) 11: /64 clock (n = 3) for the relation between the bit rate register setting and the baud rate, see section 11.3.8, bit rate register (brr). n is the decimal display of the value of n in brr (see section 11.3.8, bit rate register (brr)). 11.3.6 serial control register (scr) scr performs enabling or disabling of sci transfer operations and interrupt requests, and selection of the transfer/receive clock source. for details on interrupt requests, refer to section 11.5, interrupt sources. bit bit name initial value r/w description 7 tie 0 r/w transmit interrupt enable when this bit is set to 1, txi interrupt request is enabled. txi interrupt request cancellation can be performed by reading 1 from the tdre flag, then clearing it to 0, or clearing the tie bit to 0. 6 rie 0 r/w receive interrupt enable when this bit is set to 1, rxi and eri interrupt requests are enabled. rxi and eri interrupt request cancellation can be performed by reading 1 from the rdrf flag, or the fer, per, or orer flag, then clearing the flag to 0, or by clearing the rie bit to 0.
rev. 2.00, 03/04, page 296 of 534 bit bit name initial value r/w description 5 te 0 r/w transmit enable when this bit s set to 1, trans mission is enabled. in this state, serial transmission is started when transmit data is written to tdr and the tdre flag in ssr is cleared to 0. smr setting must be performed to decide the transfer format before setting the te bit to 1. the tdre flag in ssr is fixed at 1 if transmission is disabled by clearing this bit to 0. 4 re 0 r/w receive enable when this bit is set to 1, reception is enabled. serial reception is started in this state when a start bit is detected in asynchronous mode. smr setting must be performed to decide the transfer format before setting the re bit to 1. clearing the re bit to 0 does not affect the rdrf, fer, per, and orer flags, which retain their states. 3 ? 0 r/w reserved the initial value should not be changed. 2 teie 0 r/w transmit end interrupt enable when this bit is set to 1, tei interrupt request is enabled. tei cancellation can be performed by reading 1 from the tdre flag in ssr, then clearing it to 0 and clearing the tend flag to 0, or by clearing the teie bit to 0. 1 0 cke1 cke0 0 0 r/w r/w clock enable 1 and 0 selects the clock source. asynchronous mode 0x: on-chip baud rate generator 1x: setting prohibited legend: x: don't care
rev. 2.00, 03/04, page 297 of 534 11.3.7 serial status register (ssr) ssr is a register containing status flags of the sci. flags tdre, rdrf, orer, per, and fer can only be cleared. bit bit name initial value r/w description 7 tdre 1 r/(w) * transmit data register empty indicates whether tdr contains transmit data. [setting conditions] ? when the te bit in scr is 0 ? when data is transferred from tdr to tsr, and data writing to tdr is enabled. [clearing condition] ? when 0 is written to tdre after reading tdre = 1 6 rdrf 0 r/(w) * receive data register full indicates that the received data is stored in rdr. [setting condition] ? when serial reception ends normally and receive data is transferred from rsr to rdr [clearing condition] ? when 0 is written to rdrf after reading rdrf = 1 the rdrf flag is not affected and retains its previous value when the re bit in scr is cleared to 0. exercise care because if reception of the next data is completed while the rdrf flag is set to 1, an overrun error occurs and receive data will be lost.
rev. 2.00, 03/04, page 298 of 534 bit bit name initial value r/w description 5 orer 0 r/(w) * overrun error indicates that an overrun error occurred while receiving and the reception has ended abnormally. [setting condition] ? when the next serial reception is completed while rdrf = 1 the receive data prior to the overrun error is retained in rdr, and the data received subsequently is lost. also, subsequent serial reception cannot be continued while the orer flag is set to 1. [clearing condition] ? when 0 is written to orer after reading orer = 1 the orer flag is not affected and retains its previous state when the re bit in scr is cleared to 0. 4 fer 0 r/(w) * framing error indicates that a framing error occurred while receiving in asynchronous mode and the reception has ended abnormally. [setting condition] ? when the stop bit is 0 in 2-stop-bit mode, only the first stop bit is checked for a value of 0; the second stop bit is not checked. if a framing error occurs, the receive data is transferred to rdr but the rdrf flag is not set. also, subsequent serial reception cannot be continued while the fer flag is set to 1. [clearing condition] ? when 0 is written to fer after reading fer = 1 the fer flag is not affected and retains its previous state when the re bit in scr is cleared to 0.
rev. 2.00, 03/04, page 299 of 534 bit bit name initial value r/w description 3 per 0 r/(w) * parity error indicates that a parity error occurred while receiving in asynchronous mode and the reception has ended abnormally. [setting condition] ? when a parity error is detected during reception if a parity error occurs, the receive data is transferred to rdr but the rdrf flag is not set. also, subsequent serial reception cannot be continued while the per flag is set to 1. [clearing condition] ? when 0 is written to per after reading per = 1 the per flag is not affected and retains its previous state when the re bit in scr is cleared to 0. 2 tend 1 r transmit end [setting conditions] ? when the te bit in scr is 0 ? when tdre = 1 at transmission of the last bit of a 1-byte serial transmit character [clearing condition] ? when 0 is written to tdre after reading tdre = 1 1, 0 ? all 0 r/w reserved the initial value should not be changed. note: * only 0 can be written to clear the flag.
rev. 2.00, 03/04, page 300 of 534 11.3.8 bit rate register (brr) brr is an 8-bit register that adjusts the bit rate. as the sci performs baud rate generator control independently for each channel, different bit rates can be set for each channel. table 11.2 shows the relationships between the n setting in brr and bit rate b for asynchronous mode. the initial value of brr is h'ff, and it can be read or written to by the cpu at all times. table 11.2 relationships between n setting in brr and bit rate b mode bit rate error asynchronous mode b = 64 2 2n ? 1 (n + 1) 10 6 error (%) = { b 64 2 2n ? 1 (n + 1) ? 1 } 100 10 6 note: b: bit rate (bit/s) n: brr setting for baud rate generator (0 n 255) : operating frequency (mhz) n: determined by the smr settings shown in the following tables. smr setting cks1 cks0 n 0 0 0 0 1 1 1 0 2 1 1 3 table 11.3 shows sample n settings in brr in asynchronous mode. table 11.4 shows the maximum bit rate for each frequency in asynchronous mode.
rev. 2.00, 03/04, page 301 of 534 table 11.3 brr settings for various bit rates (asynchronous mode) (1) operating frequency (mhz) 10 12 12.288 bit rate (bit/s) n n error (%) n n error (%) n n error (%) 110 2 177 ?0.25 2 212 0.03 2 217 0.08 150 2 129 0.16 2 155 0.16 2 159 0.00 300 2 64 0.16 2 77 0.16 2 79 0.00 600 1 129 0.16 1 155 0.16 1 159 0.00 1200 1 64 0.16 1 77 0.16 1 79 0.00 2400 0 129 0.16 0 155 0.16 0 159 0.00 4800 0 64 0.16 0 77 0.16 0 79 0.00 9600 0 32 ?1.36 0 38 0.16 0 39 0.00 19200 0 15 1.73 0 19 ?2.34 0 19 0.00 31250 0 9 0.00 0 11 0.00 0 11 2.40 38400 0 7 1.73 0 9 ?2.34 0 9 0.00 operating frequency (mhz) 14 14.7456 16 17.2032 bit rate (bit/s) n n error (%) n n error (%) n n error (%) n n error (%) 110 2 248 ?0.17 3 64 0.70 3 70 0.03 3 75 0.48 150 2 181 0.16 2 191 0.00 2 207 0.16 2 223 0.00 300 2 90 0.16 2 95 0.00 2 103 0.16 2 111 0.00 600 1 181 0.16 1 191 0.00 1 207 0.16 1 223 0.00 1200 1 90 0.16 1 95 0.00 1 103 0.16 1 111 0.00 2400 0 181 0.16 0 191 0.00 0 207 0.16 0 223 0.00 4800 0 90 0.16 0 95 0.00 0 103 0.16 0 111 0.00 9600 0 45 ?0.93 0 47 0.00 0 51 0.16 0 55 0.00 19200 0 22 ?0.93 0 23 0.00 0 25 0.16 0 27 0.00 31250 0 13 0.00 0 14 ?1.70 0 15 0.00 0 16 1.20 38400 ? ? ? 0 11 0.00 0 12 0.16 0 13 0.00
rev. 2.00, 03/04, page 302 of 534 table 11.3 brr settings for various bit rates (asynchronous mode) (2) operating frequency (mhz) 18 19.6608 20 25 bit rate (bit/s) n n error (%) n n error (%) n n error (%) n n error (%) 110 3 79 ?0.12 3 86 0.31 3 88 ?0.25 3 110 ?0.02 150 2 233 0.16 2 255 0.00 3 64 0.16 3 80 ?0.47 300 2 116 0.16 2 127 0.00 2 129 0.16 2 162 0.15 600 1 233 0.16 1 255 0.00 2 64 0.16 2 80 ?0.47 1200 1 116 0.16 1 127 0.00 1 129 0.16 1 162 0.15 2400 0 233 0.16 0 255 0.00 1 64 0.16 1 80 ?0.47 4800 0 116 0.16 0 127 0.00 0 129 0.16 0 162 0.15 9600 0 58 ?0.69 0 63 0.00 0 64 0.16 0 80 ?0.47 19200 0 28 1.02 0 31 0.00 0 32 ?1.36 0 40 ?0.76 31250 0 17 0.00 0 19 ?1.70 0 19 0.00 0 24 0.00 38400 0 14 ?2.34 0 15 0.00 0 15 1.73 0 19 1.73 operating frequency (mhz) 30 33 bit rate (bit/s) n n error (%) n n error (%) 110 3 132 0.13 3 145 0.33 150 3 97 ?0.35 3 106 0.39 300 2 194 0.16 2 214 ?0.07 600 2 97 ?0.35 2 106 0.39 1200 1 194 0.16 1 214 ?0.07 2400 1 97 ?0.35 1 106 0.39 4800 0 194 0.16 0 214 ?0.07 9600 0 97 ?0.35 0 106 0.39 19200 0 48 ?0.35 0 53 ?0.54 31250 0 29 0 0 32 0 38400 0 23 1.73 0 26 ?0.54
rev. 2.00, 03/04, page 303 of 534 table 11.4 maximum bit rate for ea ch frequency (asynchronous mode) (mhz) maximum bit rate (bit/s) n n 10 312500 0 0 12 375000 0 0 12.288 384000 0 0 14 437500 0 0 14.7456 460800 0 0 16 500000 0 0 17.2032 537600 0 0 18 562500 0 0 19.6608 614400 0 0 20 625000 0 0 25 781250 0 0 30 937500 0 0 33 1031250 0 0
rev. 2.00, 03/04, page 304 of 534 11.4 operation in asynchronous mode figure 11.2 shows the general format for asynchronous serial communication. one frame consists of a start bit (low level), followed by transfer data, a parity bit, and finally stop bits (high level). in asynchronous serial communication, the transmission line is usually held in the mark state (high level). the sci monitors the transmission line, an d when it goes to the space state (low level), recognizes a start bit and starts serial communication. in asynchronous serial communication, the communication line is usually held in the mark state (high level). the sci monitors the communication line, and when it go es to the space state (low leve l), recognizes a start bit and starts serial communication. inside the sci, th e transmitter and receiver are independent units, enabling full-duplex communication. both the tr ansmitter and the receiver also have a double- buffered structure, so that data can be read or written during transmission or reception, enabling continuous data transfer. lsb start bit msb idle state (mark state) stop bit(s) 0 transmit/receive data d0 d1 d2 d3 d4 d5 d6 d7 0/1 1 1 1 1 serial data parity bit 1 bit 1 or 2 bits 7 or 8 bits 1 bit, or none one unit of transfer data (character or frame) figure 11.2 data format in asynchronous communication (example with 8-bit data, parity, two stop bits)
rev. 2.00, 03/04, page 305 of 534 11.4.1 data transfer format table 11.5 shows the data transfer formats that can be used in asynchronous mode. any of eight transfer formats can be selected according to the smr setting. table 11.5 serial transfer formats (asynchronous mode) pe 0 0 1 1 0 0 1 1 s 8-bit data stop s 7-bit data stop s 8-bit data stop stop s 8-bit data p stop s 7-bit data stop p s 7-bit data stop stop chr 0 0 0 0 1 1 1 1 stop 0 1 0 1 0 1 0 1 smr settings 123456789101112 serial transfer format and frame length stop s 8-bit data p stop s 7-bit data stop p stop [legend] s: start bit stop: stop bit p: parity bit
rev. 2.00, 03/04, page 306 of 534 11.4.2 receive data samplin g timing and reception marg in in asynchronous mode in asynchronous mode, the sci operates on a basic clock with a frequency of 16 times the bit rate. in reception, the sci samples the falling edge of the start bit using the basic clock, and performs internal synchronization. receive data is latched at the middle of each bit by sampling the data at the rising edge of the 8th pulse of the basic clock as shown in figure 11.3. thus the reception margin in asynchronous mode is given by formula (1) below. m = { (0.5 ? ) ? (l ? 0.5) f ? (1 + f) } 100 [%] 1 2n d ? 0.5 n ... formula (1) where m: reception margin n: ratio of bit rate to clock (n = 16) d: clock duty cycle (d = 0.5 to 1.0) l: frame length (l = 9 to 12) f: absolute value of clock rate deviation assuming values of f = 0 and d = 0.5 in formula (1), a reception margin is given by formula below. m = {0.5 ? 1/(2 16)} 100 [%] = 46.875% however, this is only the computed value, and a margin of 20% to 30% should be allowed in system design. internal base clock 16 clocks 8 clocks receive data (rxd) synchronization sampling timing start bit d0 d1 data sampling timing 15 0 7 15 0 0 7 figure 11.3 receive data sampling timing in asynchronous mode
rev. 2.00, 03/04, page 307 of 534 11.4.3 clock an internal clock generated by the on-chip baud ra te generator can be selected as the sci?s serial clock, according to the setting of the c/ a bit in smr and the cke1 and cke0 bits in scr. 11.4.4 sci initializatio n (asynchronous mode) before transmitting and receiving da ta, you should first clear the te an d re bits in scr to 0, then initialize the sci as shown in figure 11.4. when the operating mode, transfer format, etc., is changed, the te and re bits must be cleared to 0 before making the change. when the te bit is cleared to 0, the tdre flag is set to 1. note th at clearing the re bit to 0 does not initialize the contents of the rdrf, per, fer, and orer flags, or the contents of rdr. wait start of initialization set data transfer format in smr [1] set cke1 and cke0 bits in scr (te, re bits = 0) no yes set value in brr clear te and re bits in scr to 0 [2] [3] set te and re bits in scr to 1, and set rie, tie, and teie bits [4] 1-bit interval elapsed? [1] set the clock selection in scr. be sure to clear bits rie, tie, and teie, and bits te and re, to 0. when the clock is selected in asynchronous mode, it is output immediately after scr settings are made. [2] set the data transfer format in smr. [3] write a value corresponding to the bit rate to brr. (not necessary if an external clock is used.) [4] wait at least one bit interval, then set the te bit or re bit in scr to 1. also set the rie, tie, and teie bits. setting the te and re bits enables the txd and rxd pins to be used. figure 11.4 sample sci initialization flowchart
rev. 2.00, 03/04, page 308 of 534 11.4.5 data transmission (asynchronous mode) figure 11.5 shows an example of the operation for transmission in asynchronous mode. in transmission, the sci operates as described below. 1. the sci monitors the tdre flag in ssr, and if is cleared to 0, recognizes that data has been written to tdr, and transfers the data from tdr to tsr. 2. after transferring data from tdr to tsr, the sci sets the tdre flag to 1 and starts transmission. if the tie bit is set to 1 at this time, a transmit data empty interrupt request (txi) is generated. because the txi in terrupt routine writes the next transmit data to tdr before transmission of the current transmit data has fi nished, continuous transmission can be enabled. 3. data is sent from the txd pin in the following order: start bit, transmit data, parity bit (may be omitted depending on the format), and stop bit. 4. the sci checks the tdre flag at the timing for sending the stop bit. 5. if the tdre flag is 0, the data is transferred from tdr to tsr, the stop bit is sent, and then serial transmission of the next frame is started. 6. if the tdre flag is 1, the tend flag in ssr is set to 1, the stop bit is sent, and then the "mark state" is entered in which 1 is output. if the te ie bit in scr is set to 1 at this time, a tei interrupt request is generated. figure 11.6 shows a sample flowchart fo r transmission in asynchronous mode. tdre tend 0 1 frame d0 d1 d7 0/1 1 0 d0 d1 d7 0/1 1 1 1 data start bit parity bit stop bit start bit data parity bit stop bit txi interrupt request generated data written to tdr and tdre flag cleared to 0 in txi interrupt handling routine tei interrupt request generated idle state (mark state) txi interrupt request generated figure 11.5 example of operation in transmission in asynchronous mode (example with 8-bit data, parity, one stop bit)
rev. 2.00, 03/04, page 309 of 534 no [1] yes initialization start of transmission read tdre flag in ssr [2] write transmit data to tdr and clear tdre flag in ssr to 0 no yes no yes read tend flag in ssr [3] clear te bit in scr to 0 tdre = 1? all data transmitted? tend = 1? [1] sci initialization: the txd pin is automatically designated as the transmit data output pin. after the te bit is set to 1, a frame of 1s is output, and transmission is enabled. [2] sci status check and transmit data write: read ssr and check that the tdre flag is set to 1, then write transmit data to tdr and clear the tdre flag to 0. [3] serial transmission continuation procedure: to continue serial transmission, read 1 from the tdre flag to confirm that writing is possible, then write data to tdr, and then clear the tdre flag to 0. figure 11.6 sample serial transmission flowchart
rev. 2.00, 03/04, page 310 of 534 11.4.6 serial data recep tion (asynchronous mode) figure 11.7 shows an example of the operation for reception in asynchronous mode. in serial reception, the sci operates as described below. 1. the sci monitors the communication line, and if a start bit is detected, performs internal synchronization, receives receive data in rsr, and checks the parity bit and stop bit. 2. if an overrun error (when reception of the next data is completed while the rdrf flag is still set to 1) occurs, the orer bit in ssr is set to 1. if the rie bit in scr is set to 1 at this time, an eri interrupt request is generated. receive da ta is not transferred to rdr. the rdrf flag remains to be set to 1. 3. if a parity error is detected, the per bit in ss r is set to 1 and receive data is transferred to rdr. if the rie bit in scr is set to 1 at this time, an eri interrupt request is generated. 4. if a framing error (when the stop bit is 0) is detected, the fer bit in ssr is set to 1 and receive data is transferred to rdr. if the rie bit in scr is set to 1 at this time, an eri interrupt request is generated. 5. if reception finishes successful ly, the rdrf bit in ssr is se t to 1, and receive data is transferred to rdr. if the rie bit in scr is set to 1 at this time, an rxi interrupt request is generated. because the rxi interrupt routine reads the receive data transferred to rdr before reception of the next receive data has fini shed, continuous reception can be enabled. rdrf fer 0 1 frame d0 d1 d7 0/1 1 0 d0 d1 d7 0/1 0 1 1 data start bit parity bit stop bit start bit data parity bit stop bit rxi interrupt request generated eri interrupt request generated by framing error idle state (mark state) rdr data read and rdrf flag cleared to 0 in rxi interrupt handling routine figure 11.7 example of sci operation in reception (example with 8-bit data, parity, one stop bit)
rev. 2.00, 03/04, page 311 of 534 table 11.6 shows the states of th e ssr status flags and receive da ta handling when a receive error is detected. if a receive error is detected, the rdrf flag retains its state before receiving data. reception cannot be resumed while a receive error fl ag is set to 1. accordingly, clear the orer, fer, per, and rdrf bits to 0 before resuming reception. figure 11.8 shows a sample flowchart for serial data reception. table 11.6 ssr status flag s and receive data handling ssr status flag rdrf * orer fer per receive data receive error type 1 1 0 0 lost overrun error 0 0 1 0 transferred to rdr framing error 0 0 0 1 transferred to rdr parity error 1 1 1 0 lost overrun error + framing error 1 1 0 1 lost overrun error + parity error 0 0 1 1 transferred to rdr framing error + parity error 1 1 1 1 lost overrun error + framing error + parity error note: the rdrf flag retains its state before data reception.
rev. 2.00, 03/04, page 312 of 534 yes [1] no initialization start of reception [2] no yes read rdrf flag in ssr [4] [5] clear re bit in scr to 0 read orer, per, and fer flags in ssr error handling (continued on next page) [3] read receive data in rdr, and clear rdrf flag in ssr to 0 no yes per fer orer = 1? rdrf = 1? all data received? sci initialization: the rxd pin is automatically designated as the receive data input pin. receive error handling: if a receive error occurs, read the orer, per, and fer flags in ssr to identify the error. after performing the appropriate error processing, ensure that the orer, per, and fer flags are all cleared to 0. reception cannot be resumed if any of these flags are set to 1. sci status check and receive data read : read ssr and check that rdrf = 1, then read the receive data in rdr and clear the rdrf flag to 0. transition of the rdrf flag from 0 to 1 can also be identified by an rxi interrupt. serial reception continuation procedure: to continue serial reception, before the stop bit for the current frame is received, read the rdrf flag, read rdr, and clear the rdrf flag to 0. [1] [2] [3] [4] [5] figure 11.8 sample serial reception data flowchart (1)
rev. 2.00, 03/04, page 313 of 534 [3] error handling parity error handling clear orer, per, and fer flags in ssr to 0 no yes no yes framing error handling no yes overrun error handling orer = 1? fer = 1? per = 1? figure 11.8 sample serial reception data flowchart (2)
rev. 2.00, 03/04, page 314 of 534 11.5 interrupt sources 11.5.1 interrupts in normal seri al communication interface mode table 11.7 shows the interrupt so urces in normal serial communi cation interface mode. a different interrupt vector is assigned to each interrupt source, and individual interrupt sources can be enabled or disabled using the enable bits in scr. when the tdre flag in ssr is set to 1, a txi interrupt request is generated. when the tend flag in ssr is set to 1, a tei interrupt request is generated. when the rdrf flag in ssr is set to 1, an rxi interrupt request is generated. when the orer, per, or fer flag in ssr is set to 1, an eri in terrupt request is generated. a tei interrupt is generated when the tend flag is set to 1 while the teie bit is set to 1. if a tei interrupt and a txi interrupt are generated simultaneously, th e txi interrupt has priority for acceptance. however, note that if the tdre and tend flags are cleared simultaneously by the txi interrupt routine, the sci cannot branch to the tei interrupt routine later. table 11.7 sci interrupt sources channel name interrupt sour ce interrupt flag priority eri0 receive error orer, fer, per high rxi0 receive data full rdrf txi0 transmit data empty tdre 0 tei0 transmission end tend low
rev. 2.00, 03/04, page 315 of 534 11.6 usage notes 11.6.1 module stop mode setting sci operation can be disabled or enabled using the module stop control register. the initial setting is for sci operation to be halt ed. register access is enabled by clearing module stop mode. for details, refer to section 16, power-down modes. 11.6.2 relation between writes to tdr and the tdre flag the tdre flag in ssr is a status flag that indi cates that transmit data has been transferred from tdr to tsr. when the sci tran sfers data from tdr to tsr, the tdre flag is set to 1. data can be written to tdr regardless of the state of the tdre flag. however, if new data is written to tdr when the tdre flag is cleared to 0, the data stored in tdr will be lost since it has not yet been transferred to tsr. it is therefore e ssential to check that the tdre flag is set to 1 before writing transmit data to tdr. 11.6.3 operation in case of mode transition ? transmission operation should be stopped (by clearing te, tie, and teie to 0) before making a module stop mode or software standby mode transition. tsr, tdr, and ssr are reset. the output pin states in module stop mode or software standby mode depend on the port settings, and become high-level output after the relevant mode is cleared. if a transition is made during transmission, the data being transmitted will be undefined. when transmitting without changing the transmit mode after the relevant mode is cleared, transmission can be started by setting te to 1 again, and performing the following sequence: ssr read tdr write tdre clearance. to transmit with a different transmit mode after clearing the relevant mode, the procedure must be started again from initialization. figure 11.9 shows a sample flowchart for mode transition during transmission. ? reception receive operation should be stopped (by clearing re to 0) before making a module stop mode or software standby mode transition. rsr, rdr, and ssr are reset. if a transition is made during reception, the data being received will be invalid. to continue receivi ng without changing the reception mode after the relevant mode is cleared, set re to 1 before starting re ception. to receive with a diffe rent receive mode, the procedure must be started again from initialization. figure 11.10 shows a sample flowchart for mode transition during reception.
rev. 2.00, 03/04, page 316 of 534 read tend flag in ssr te = 0 transition to software standby mode exit from software standby mode change operating mode? no all data transmitted? tend = 1 yes yes yes no no [1] [3] [2] te = 1 initialization [1] data being transmitted is interrupted. after exiting software standby mode, normal cpu transmission is possible by setting te to 1, reading ssr, writ- ing tdr, and clearing tdre to 0. [2] if tie and teie are set to 1, clear them to 0 in the same way. [3] includes module stop mode. figure 11.9 sample flowchart for mode transition during transmission
rev. 2.00, 03/04, page 317 of 534 re = 0 transition to software standby mode read receive data in rdr read rdrf flag in ssr exit from software standby mode change operating mode? no rdrf = 1 yes yes no [1] [2] re = 1 initialization [1] receive data being received becomes invalid. [2] includes module stop mode. figure 11.10 sample flowchart for mode transition during reception
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rev. 2.00, 03/04, page 319 of 534 section 12 universal serial bus 2 (usb2) this lsi incorporates a usb2 function module supporting the usb standard. figure 12.1 shows the block diagram of the usb2. 12.1 features ? supports the usb version 2.0 usb standard requests are processed automatically (except for some requests) get descriptor, class, and vendor requests are processed by firmware ? high-speed mode and full-speed mode are supported ? supports four endpoints; ep0, ep1, ep2, and ep3 max. packet size endpoint full speed high speed fifo configuration transfer method transfer direction dma transfer ep0s 8 bytes 8 bytes single setup out ? ep0i 64 bytes 64 bytes single control in ? ep0o 64 bytes 64 bytes single control out ? ep1 64 bytes 512 bytes dual bulk out possible ep2 64 bytes 512 bytes dual bulk in possible ep3 64 bytes 64 bytes single interrupt in ? ? control, bulk, and interrupt transfers are supported ? the maximum packet size in high-speed mode and full-speed mode is switched automatically ? dma transfer interface dma transfer is enabled for endpoints 1 and 2 ? interrupt interface two interrupt requests (usbi0 and usbi1) are supported as the interrupt request output pins. each interrupt source can be assigned via the internal registers
rev. 2.00, 03/04, page 320 of 534 usclk (30 mhz) d+ d- protocol processor interrupt request dma transfer request peripheral bus external transceiver status and control register fifo utmi usb module figure 12.1 block diagram of usb2
rev. 2.00, 03/04, page 321 of 534 12.2 input/output signals table 12.1 lists the i/o signals of usb2. table 12.1 input/output signals classification symbol i/o function usb bus power supply usvbus input usb bus power supply signal this is a connection or disconnection detection pin for the usb cable. this pin is connected to the vbus pin in the usb connector. high: vbus pin = low means disconnection low: vbus pin = high means connection note: this signal should be input after the signal of the vbus pin of the usb connector is inverted. transceiver signal usclk input usb clock this is a usb clock (30 mhz) which is output by the transceiver. drvcc usrxv usrxerr usrxact ustxrdy uslsta[1:0] input usb 2.0 transceiver input signal these signals are connected to the usb 2.0 transceiver. they are complied with the utmi specification. for details, refer to the utmi specifications. usd[15:0] uswdvld i/o usb 2.0 transceiver i/o signal these signals are connected to the usb 2.0 transceiver. they are complied with the utmi specification. for details, refer to the utmi specifications. ustsel usopm[1:0] usxcvrs ustxv ussusp output usb 2.0 transceiver output signal these signals are connected to the usb 2.0 transceiver. they are complied with the utmi specification. for details, refer to the utmi specification. monitor pin usrst output this is a monitor pin.
rev. 2.00, 03/04, page 322 of 534 12.3 register descriptions the usb2 has the following registers. ? interrupt flag register 0 (ifr0) ? interrupt select register 0 (isr0) ? interrupt enable register 0 (ier0) ? ep0o receive data size register (epsz0o) ? ep1 receive data si ze register (epsz1) ? ep0i data register (epdr0i) ? ep0o data register (epdr0o) ? ep0s data register (epdr0s) ? ep1 data register (epdr1) ? ep2 data register (epdr2) ? ep3 data register (epdr3) ? data status register 0 (dasts0) ? packet enable register 0i (pkte0i) ? packet enable register 2 (pkte2) ? packet enable register 3 (pkte3) ? fifo clear register 0 (fclr0) ? endpoint stall register 0 (epstl0) ? dma set register 0 (dma0) ? control register (ctrl) ? port function control register 3 (pfcr3) ? usb suspend status register (usbsusp)
rev. 2.00, 03/04, page 323 of 534 12.3.1 interrupt flag register 0 (ifr0) ifr0 indicates the setup request recep tion, ep0i, ep0o, ep 1, ep2, and ep3 transmission/reception, and bus reset state and mo nitors a vbus interrupt flag and usb mode interrupt flag. if the corresponding flag is set to 1, the corresponding interrupt request is output. a flag in this register can be cleared by writing 0 to it. writing 1 to a flag is invalid and causes no operation. note that the ep1full and ep2empty bits are status bits indicating the fifo states of the ep1 and ep2. therefore these bits cannot be cleared. the vbus mn and mode mn bits are also status bits so they cannot be cleared. bit bit name initial value r/w description 31 to 27 ? all 0 r reserved the write value should always be 0. 26 mode mn1 0 r usb mode status 1 this bit is a status bit which indicates the usb transfer mode. this bit is used as two bits with the mode mn0 bit. 0: at a reset or when the cable is disconnected 1: full-speed mode (12 mbps) 2: high-speed mode (480 mbps) 3: chirp mode refer to section 12.8.12, usb bus idle in high-speed mode. this bit cannot be cleared because this bit is a status bit. 25 mode mn0 0 r usb mode status 0 this bit is a status bit which indicates the usb transfer mode. this bit is used as two bits with the mode mn1 bit. this bit cannot be cleared because this bit is a status bit.
rev. 2.00, 03/04, page 324 of 534 bit bit name initial value r/w description 24 mode f 0 r/w usb transfer mode change detection [setting condition] this bit is set to 1 when the usb mode status bits are changed. [clearing conditions] ? at a reset ? when 0 is written to this bit 23 to 18 ? 0 r reserved the write value should always be 0. 17 vbus mn 0 r usb connection status this bit is a status bit whic h monitors the state of the usvbus pin. this bit reflec ts the state of the usvbus pin. 1: the usvbus pin is connected. 0: the usvbus pin is not connected. 16 vbus f 0 r/w usb connection/disconnection detection [setting condition] this bit is set to 1 when the function is connected/disconnected to/from the usb bus. [clearing conditions] ? at a reset ? when 0 is written to this bit 15 to 10 ? all 0 r reserved the write value should always be 0. 9 ep3tr 0 r/w ep3 transfer request [setting condition] this bit is set to 1 if there is no valid data in the fifo when an in token is sent from the host to ep3. [clearing conditions] ? at a reset ? when 0 is written to this bit
rev. 2.00, 03/04, page 325 of 534 bit bit name initial value r/w description 8 ep3ts 0 r/w ep3 transmit complete [setting condition] this bit is set to 1 if the data written in ep3 is transmitted to the host normally and the ack handshake is returned. [clearing conditions] ? at a reset ? when 0 is written to this bit 7 brst 0 r/w bus reset [setting condition] this bit is set to 1 when the bus reset signal is detected on the usb bus. [clearing conditions] ? at a reset ? when 0 is written to this bit 6 ep2tr 0 r/w ep2 transfer request [setting condition] this bit is set to 1 if there is no valid data in both fifos when an in token is sent from the host to ep2. [clearing conditions] ? at a reset ? when 0 is written to this bit 5 ep2empty 0 r ep2 fifo empty * 2 [setting conditions] ? at a reset ep2 has a dual fifo configuration. this bit is set to 1 if there is no valid data at leas t in the single fifo. if data is full in both fifos, this bit is set to 0. [clearing condition] this bit cannot be cleared because this bit is a status bit.
rev. 2.00, 03/04, page 326 of 534 bit bit name initial value r/w description 4 ep1full 0 r ep1 fifo full * 1 [setting condition] ep1 has a dual fifo configuration. this bit is set to 1 if data is full at least in the single fifo. if there is no valid data in both fifos, this bit is set to 0. [clearing condition] this bit cannot be cleared because this bit is a status bit. 3 setupts 0 r/w setup request receive complete [setting condition] this bit is set to 1 if ep0s normally receives 8-byte data to be decoded by the function from the host and returns the ack handshake to the host. [clearing conditions] ? at a reset ? when 0 is written to this bit 2 ep0ots 0 r/w ep0o receive complete [setting condition] this bit is set to 1 if ep0o receives data from the host normally and returns the nyet or ack handshake to the host. [clearing conditions] ? at a reset ? when 0 is written to this bit 1 ep0itr 0 r/w ep0i transfer request [setting condition] this bit is set to 1 if there is no valid data in the fifo when an in token is sent from the host to ep0i [clearing conditions] ? at a reset ? when 0 is written to this bit
rev. 2.00, 03/04, page 327 of 534 bit bit name initial value r/w description 0 ep0its 0 r/w ep0i transmit complete [setting condition] this bit is set to 1 if the data written in ep0i is transmitted to the host normally and the ack handshake is returned. [clearing conditions] ? at a reset ? when 0 is written to this bit notes: 1. fifo full in case of in fifo: the data whic h can be transmitted is in the fifo. in case of out fifo: the data which is valid is in the fifo. 2. fifo empty in case of in fifo: the data which can be transmitted is not in the fifo. in case of out fifo: the data wh ich is valid is not in the fifo.
rev. 2.00, 03/04, page 328 of 534 12.3.2 interrupt sele ct register 0 (isr0) isr0 sets interrupt requests indicated in the inte rrupt flag register. when the corresponding bit is cleared to 0, the usbi0 interrupt request is output. when the corresponding bit is set to 1, the usbi1 interrupt request is output. in the initial va lue, each interrupt source in the interrupt flag register is requested from usbi0. bit bit name initial value r/w description 31 to 25 ? all 0 r reserved the write value should always be 0. 24 mode f 0 r/w selects the mode f interrupt. 23 to 17 ? all 0 r reserved the write value should always be 0. 16 vbus f 0 r/w selects the vbus f interrupt. 15 to 10 ? all 0 r reserved the write value should always be 0. 9 ep3tr 0 r/w selects the ep3tr interrupt. 8 ep3ts 0 r/w selects the ep3ts interrupt. 7 brst 0 r/w selects the brst interrupt. 6 ep2tr 0 r/w selects the ep2tr interrupt. 5 ep2empty 0 r/w selects the ep2empty interrupt. 4 ep1full 0 r/w selects the ep1full interrupt 3 setupts 0 r/w selects the setupts interrupt. 2 ep0ots 0 r/w selects the ep0ots interrupt. 1 ep0itr 0 r/w selects the ep0itr interrupt. 0 ep0its 0 r/w selects the ep0its interrupt.
rev. 2.00, 03/04, page 329 of 534 12.3.3 interrupt enab le register 0 (ier0) ier0 enables the interrupt request indicated in the in terrupt flag register. when an interrupt flag is set while the corresponding bit in ier0 is set to 1, an interrupt request selected by the interrupt select register is asserted. bit bit name initial value r/w description 31 to 25 ? all 0 r reserved the write value should always be 0. 24 mode f 0 r/w enables the mode f interrupt. 23 to 17 ? all 0 r reserved the write value should always be 0. 16 vbus f 0 r/w enables the vbus f interrupt. 15 to 10 ? all 0 r reserved the write value should always be 0. 9 ep3tr 0 r/w enables the ep3tr interrupt. 8 ep3ts 0 r/w enables the ep3ts interrupt. 7 brst 0 r/w enables the brst interrupt. 6 ep2tr 0 r/w enables the ep2tr interrupt. 5 ep2empty 0 r/w enables the ep2empty interrupt. 4 ep1full 0 r/w enables the ep1full interrupt 3 setupts 0 r/w enables the setupts interrupt. 2 ep0ots 0 r/w enables the ep0ots interrupt. 1 ep0itr 0 r/w enables the ep0itr interrupt. 0 ep0its 0 r/w enables the ep0its interrupt. 12.3.4 ep0o receive data size register (epsz0o) epsz0o is a receive data size register for endpoint 0o. epsz0o indicates the number of bytes of data to be received from the host. bit bit name initial value r/w description 31 to 0 d31 to d0 ? r ep0o receive data size
rev. 2.00, 03/04, page 330 of 534 12.3.5 ep1 receive data size register (epsz1) epsz1 is a receive data size register for endpoint 1. epsz1 indicates the number of bytes of data to be received from the host. the fifo for endpo int 1 has a dual-fifo configuration. the data size indicated by this re gister refers to the currently selected fifo. bit bit name initial value r/w description 31 to 0 d31 to d0 ? r ep1 receive data size 12.3.6 ep0i data register (epdr0i) epdr0i is a 64-byte transmit fifo buffer for endpoint 0. epdr0i stores number of packets of transmit data for control-in. if one packet of data is written and number of transmit data is written in the packet enable register 0i (pkte0i), transmit data is valid. if data is transmitted and then the ack handshake is returned from the host, the ep0its bit in ifr0 is set. epdr0i can be initialized by setting the ep0iclr bit in the fifo clear register 0. when the setup is received, epdr0i is cleared. after the setup data is received, transm ission is impossible until the setup ts bit is cleared. bit bit name initial value r/w description 31 to 0 d31 to d0 all 0 w 64-byte transmit fifo buffer for ep0 12.3.7 ep0o data register (epdr0o) epdr0o is a 64-byte receive fi fo buffer for endpoint 0 and ha s a single fifo buffer. when reception is completed, the usb returns th e nyet handshake (high-speed mode) or ack handshake (full-speed mode) to the host. epdr0o stores receive data for endpoint 0 except for the setup request. when data is received normally, th e ep0ots bit in ifr0 is set and the number of receive bytes is indicated in the ep0o receive data size register. after the setup data is received, reception is impossible until th e setup ts bit is cleared. though the 0-length packet can be received, the ack handshake (both high -speed and full-speed modes) is returned to the host and data is igno red. however, the ep0ots flag in ifr0 is set. bit bit name initial value r/w description 31 to 0 d31 to d0 all 0 r 64-byte receive fifo buffer for ep0
rev. 2.00, 03/04, page 331 of 534 12.3.8 ep0s data register (epdr0s) epdr0s is a data register only for the setup request for endpoint 0. epdr0s stores 8-byte request data sent from the host in setup stage. note that only request data to be processed by the microcomputer is received. when a request processed by the usb au tomatically is received, data is not stored. when data reception is started in the next setup stage during reading, data is overwritten unconditionally. bit bit name initial value r/w description 31 to 0 d31 to d0 all 0 r data register only for ep0 setup request 12.3.9 ep1 data register (epdr1) epdr1 consists of two 512-byte receive fifo bu ffers for endpoint 1. the size of epdr1 is as twice as the maximum packet size in high-speed mode and has a dual-fifo configuration. when there is no data in the single fifo buffer, the usb returns the ack handshake (both high-speed and full-speed modes) to the host. when reception is completed and data is full in the both fifo buffers, the usb returns the nyet handshake (high-speed mode) or ack handshake (full-speed mode) to the host. the number of receive bytes is indicated in epsz1. dma transfer can be performed for receive data in ep dr1. epdr1 can be initialized by setting the ep1clr bit in the fifo clear register 0. though the 0-length packet can be received, the fifo is not full, the ack handshake (both high- speed and full-speed modes) is returned to the host, and data is ignored. therefore the ep1 full status flag in ifr0 is not set. bit bit name initial value r/w description 31 to 0 d31 to d0 all 0 r two 512-byte receive fifo buffers for ep1 12.3.10 ep2 data register (epdr2) epdr2 consists of two 512-byte transmit fifo buffer for endpoint 2. the size of epdr2 is as twice as the maximum packet size in high-speed mode and has a dual-fifo configuration. when transmit data is written in epdr2 and number of transmit data is written in the packet enable register 2 (pkte2), one packet of transmit data is valid and the buffer is switched. dma transfer can be performed for transmit data to epdr2. epdr2 can be initialized by setting the ep2clr bit in the fifo clear register 0.
rev. 2.00, 03/04, page 332 of 534 bit bit name initial value r/w description 31 to 0 d31 to d0 all 0 w 512-byte transmit fifo buffer for ep2 12.3.11 ep3 data register (epdr3) epdr3 is a 64-byte transmit fifo buffer for endpoint 3. epdr3 stores one packet of transmit data in the interrupt transfer for endpoint 3. if on e packet of data is writte n and number of transmit data is written in the packet enable register 3 (pkte3 ), transmit data is valid. if one packet of data is transmitted normally and the ack handshake is returned from the host, the ep3ts bit in ifr0 is set. epdr3 can be initialized by setting the ep3clr bit in the fifo clear register 0. bit bit name initial value r/w description 31 to 0 d31 to d0 all 0 w 64-byte transmit fifo buffer for ep3 12.3.12 data status register 0 (dasts0) dasts0 indicates whether the in fifo data registers contain valid data or not. a bit in dasts0 is set to 1 when data written to the correspondi ng in fifo becomes valid after the number of transfer bytes is written in the pa cket enable register. a bit in dasts0 is cleared to 0 when all valid data is sent to the host. for endpoint 2, having a dual-fifo configuration, the corresponding bit in dasts0 is cleared to 0 when both fifos become empty. bit bit name initial value r/w description 31 to 6 ? all 0 r reserved the write value should always be 0. 5 ep3de 0 r ep3 data enable set to 1 when ep3 contains valid data and cleared to 0 when ep3 contains no valid data. 4 ep2de 0 r ep2 data enable set to 1 when ep2 contains valid data and cleared to 0 when ep2 contains no valid data. 3 to 1 ? all 0 r reserved the write value should always be 0. 0 ep0ide 0 r ep0i data enable set to 1 when ep0i contains valid data and cleared to 0 when ep0i contains no valid data.
rev. 2.00, 03/04, page 333 of 534 12.3.13 packet enable register 0i (pkte0i) the number of transmit data is written in pkte0 i after writing transmit data in epdr0i. then transmit data becomes valid and data is transmitted by the next in token. data is not transmitted only by writing data in epdr0i. the number of data bytes written in epdr0i must match the number of transmit data bytes to be written in pkte0i. bit bit name initial value r/w description 31 to 0 d31 to d0 all 0 w number of transmit data 12.3.14 packet enable register 2 (pkte2) the number of transmit data is written in pkte2 after writing transmit data in epdr2. then transmit data becomes valid and data is transmitted by the next in token. data is not transmitted only by writing data in epdr2. the number of data bytes written in epdr2 must ma tch the number of transmit data bytes to be written in pkte2. bit bit name initial value r/w description 31 to 0 d31 to d0 all 0 w number of transmit data 12.3.15 packet enable register 3 (pkte3) the number of transmit data is written in pk te3 after writing transmit data in epdr3. then transmit data becomes valid and data is transmitted by the next in token. data is not transmitted only by writing data in epdr3. the number of data bytes written in epdr3 must match the number of transmit data bytes to be written in pkte3. bit bit name initial value r/w description 31 to 0 d31 to d0 all 0 w number of transmit data
rev. 2.00, 03/04, page 334 of 534 12.3.16 fifo clear register 0 (fclr0) fclr0 is a one-shot register used to clear the fifo for each endpoint. writing 1 to a bit clears the data in the corresponding fifo. for in fifo, writing 1 to a bit in fclr0 clears the data for which the corresponding bit in the packet enable register is not set to 1 after data write, or data that is validated by setting the corresponding bit in the packet enable register. for out fifo, writing 1 to a bit in fclr0 clears data that has been received. ep2 having a dual- fifo configuration is cleared by entire fifos. similarly, as for ep1 fifo with a dual-fifo configuration, the only side currently selected is cleared. note that this tr igger does not clear the corresponding interrupt flag. accordingly, care must be taken not to clear data that is currently being received or transmitted. bits 6, 5, and 0 are also used as the status bits. the function of the status bit is described in the lower column of the bit description. bit bit name initial value r/w description 31 to 7 ? all 0 w reserved the write value should always be 0. w ep3 clear 1 is written when clearing ep3 in fifo. writing 0 is invalid and no operation is performed. 6 ep3clr 0 r ep3 fifo clear status [setting condition] this bit is set to 1 when the ep3 fifo is forcibly cleared by the fclr register. when this bit is set to 1, access to the ep3 fifo is prohibited. this bit is cleared to 0 automatically after the fifo is internally cleared. confirm that this bit is cleared to 0 and then wait for at least four cycles, before accessing to the ep3. [clearing condition] this bit cannot be cleared because this bit is a status bit.
rev. 2.00, 03/04, page 335 of 534 bit bit name initial value r/w description w ep2 clear 1 is written when clearing ep2 in fifo. writing 0 is invalid and no operation is performed. 5 ep2clr 0 r ep2 fifo clear status [setting condition] this bit is set to 1 when the ep2 fifo is forcibly cleared by the fclr register. when this bit is set to 1, access to the ep2 fifo is prohibited. this bit is cleared to 0 automatically after the fifo is internally cleared. confirm that this bit is cleared to 0 and then wait for at least four cycles, before accessing to the ep2. [clearing condition] this bit cannot be cleared because this bit is a status bit. 4 ep1clr 0 w ep1 clear 1 is written when clearing ep1 out fifo. writing 0 is invalid and no operation is performed. 3, 2 ? all 0 w reserved the write value should always be 0. 1 ep0oclr 0 w ep0o clear 1 is written when clearing ep0o out fifo. writing 0 is invalid and no operation is performed. w ep0i clear 1 is written when clearing ep0i in fifo. writing 0 is invalid and no operation is performed. 0 ep0iclr 0 r ep0i fifo clear status [setting condition] this bit is set to 1 when the ep0i fifo is forcibly cleared by the fclr register. when this bit is set to 1, access to the ep0i fifo is prohibited. this bit is cleared to 0 automatically after the fifo is internally cleared. confirm that this bit is cleared to 0 and then wait for at least four cycles, before accessing to the ep0i. [clearing condition] this bit cannot be cleared because this bit is a status bit.
rev. 2.00, 03/04, page 336 of 534 12.3.17 endpoint stall register 0 (epstl0) epstl0 is used to stall each en dpoint. when 1 is written in a bit, the corresponding endpoint returns a stall handshake to the host, following from the next transfer. the stall bit for endpoint 0 is cleared automatically on recep tion of 8-byte request data for which decoding is performed by the function, and thus the ep0 stl bit is cleared to 0. when the setup ts flag in ifr0 is set to 1, a write of 1 to the ep0 stl bit is ignored. fo r details, refer to section 12.5.8, stall operations. when the asce bit in ctrl is set to 1, the epxs tl (x = 0, 1, 2, 3) bit is automatically cleared. for details, refer to section 12.3.19, control register (ctrl). bit bit name initial value r/w description 31 to 4 ? all 0 r reserved the write value should always be 0. 3 ep3stl 0 r/w ep3 stall sets the ep3 stall state. 2 ep2stl 0 r/w ep2 stall sets the ep2 stall state. 1 ep1stl 0 r/w ep1 stall sets the ep1 stall state. 0 ep0stl 0 r/w ep0 stall sets the ep0 stall state. 12.3.18 dma set register 0 (dma0) dma0 is set when the dmac dual address transfer is used for data registers for endpoints 1 and 2. for endpoint 1, if 1 is written in the ep1 dmae b it, the transfer is requested to the dmac when the ep1 fifo is full at least in the single fifo. that is, when th ere is valid receive data in the fifo, the transfer is requested to the dmac. when all receive da ta is read and both fifos are empty, the transfer is not requested to the dmca any more. for endpoint 2, if 1 is written in the ep2 dmae b it, the transfer is requested to the dmac when the ep2 fifo is empty at least in the single fifo. that is, when there is no valid data in the fifo even with one side, the transfer is requeste d to the dmac. when data is written by the microcomputer and both fifos are full, the transfer is not requested to the dmca any more. since an interrupt request is not masked auto matically, the ep1 full and ep2 empty bits in ier0 are cleared to 0 and an interrupt should not be requested by an interrupt pin.
rev. 2.00, 03/04, page 337 of 534 bit bit name initial value r/w description 31 to 2 ? all 0 r reserved the write value should always be 0. 1 ep2dmae 0 r/w ep2 dma enable enables the dma transfer for ep2. 0 ep1dmae 0 r/w ep1 dma enable enables the dma transfer for ep1. 12.3.19 control register (ctrl) ctrl controls the usb module. bit bit name initial value r/w description 31 to 2 ? all 0 r reserved the write value should always be 0. 1 asce 0 r/w automatic stall clear enable when this bit is set to 1, the stall handshake is returned to the host and then the stall se t bit (epxstl (x = 0, 1, 2, 3) bit in epstl0) for the returned endpoint is automatically cleared. the aut omatic stall clear enabling is common to all endpoints. this function cannot be controlled individually for each endpoint. when this bit is cleared to 0, the epxstl (x = 0, 1, 2, 3) bit is not automatically cleared. the user needs to clear the epxstl (x = 0, 1, 2, 3) bit. to enable this bit, this bit should be set to 1 before the epxstl (x = 0, 1, 2, 3) bit in epstl0 is set to 1. 0 pullupe 0 r/w pull-up enable controls pull-up of the phy complying with the utmi. if 1 is written in this bit, pull- up is enabled for the phy.
rev. 2.00, 03/04, page 338 of 534 12.3.20 port function co ntrol register 3 (pfcr3) pfcr3 controls the usb software reset and suspend reset. bit bit name initial value r/w description 7 susrif 0 r/w suspend recover interrupt flag for details on operation, refer to section 12.7.2, software standby in suspend mode. 6 susrie 0 r/w suspend recover interrupt enable for details on operation, refer to section 12.7.2, software standby in suspend mode. 5 to 1 ? all 0 r/w reserved these bits can be read from or written to. however, the write value should always be 0. 0 usbswrst 0 r/w usb module software reset while this bit is set to 1, the usb module is in the reset state. 12.3.21 usb suspend status register (usbsusp) usbsusp specifies the usb stat e and enables or disables a usb suspend interrupt request. usbsusp is initialized to h'00 at a reset or in hardware standby mode. bit bit name initial value r/w description 7 ususmoni 0 r * 1 usb suspend monitor this bit is a monitor bit that indicates whether the usb is in the normal state or in the suspend state. this bit can be read from but cannot be modified. 0: indicates that the usb is in the normal state. 1: indicates that the usb is in the suspend state.
rev. 2.00, 03/04, page 339 of 534 bit bit name initial value r/w description 6 ususfg 0 r/(w) * 2 usb suspend interrupt (usbi2) flag this bit is a status flag that indicates the transition from the normal state to the suspend state is made. [clearing condition] while ususfg = 1, 0 is written to ususfg after reading ususfg [setting condition] when transition from the nor mal state to the suspend state is made 5 ususfge 0 r/w usb suspend interrupt (usbi2) enable enables or disables the usb suspend interrupt (usbi2) request to the cpu. 0: the usb suspend interrupt (usbi2) request is disabled. 1: the usb suspend interrupt (usbi2) request is enabled. 4 ususout 0 r/w usb suspend output enable enables or disables the suspend state notification to the external transceiver when the usb enters the suspend state. 0: not notified that the usb enters the suspend state to the external transceiver. the external pin, ussusp , is always set to 1. 1: notified that the usb enter s the suspend state to the external transceiver. when the usb is in the suspend state, the external pin, ussusp , is cleared to 0. 3 to 0 ? all 0 r/w reserved the initial value should not be changed. notes: 1. cannot be modified. 2. only 0 can be written after reading 1 to clear the flag.
rev. 2.00, 03/04, page 340 of 534 12.4 interrupt pins this module has two interrupt sources. the interr upt select register 0 is used to set the correspondence between interrupt flags and interrupt sources (usbi1 and usbi0). basically, all processing is possible by using only one interrupt source. if there is an interrupt source whose response needs to be fast, priority can be set by using the second interrupt source. among interrupt sources of this module, an interrup t source related to endpoint 0 (bits 3 to 0 in ifr0) must be assigned to the same interrupt source. 12.4.1 usbi0 interrupt the usbi0 is an interrupt request for an interrupt source in which 0 is set by the interrupt select register 0. among interrupt sources assigned to the usbi0, when only one of a corresponding bit in the interrupt flag register 0 is se t to 1, an interrupt request occurs. 12.4.2 usbi1 interrupt the usbi1 is an interrupt request for an interrupt source in which 1 is set by the interrupt select register 0. among interrupt sources assigned to the usbi1, when only one of a corresponding bit in the interrupt flag register 0 is se t to 1, an interrupt request occurs.
rev. 2.00, 03/04, page 341 of 534 12.5 communication operation 12.5.1 usb cable connection if the usb cable enters the connection state from th e disconnection state, pe rform the operation as shown in figure 12.2. ye s during usb cable disconnection usvbus pin = high mode mn 0/1 in ifr0 = 00 clear interrupt flag (vbus f in ifr0 = 0) write 1 to pullupe bit (pullupe in ctrl = 1) clear interrupt flag (brst in ifr0 = 0) clear all fifos (ep0i/0o/1/2/3 clr in fclr0 = 1) usb cable connection vbus f in ifr0 = 1 vbus mn in ifr0 = 1 mode mn 0/1 in ifr0 = 01 d+ pull-up on interrupt generated interrupt generated is charp received? wait for control transfer receive bus reset brst in ifr0 = 1 transmit charp mode mn 0/1 in ifr0 = 11 high-speed mode mode mn 0/1 in ifr0 = 10 full-speed mode mode mn 0/1 in ifr0 = 01 usb function firmware no figure 12.2 usb cable connection
rev. 2.00, 03/04, page 342 of 534 as not shown in figure 12.2, when the mode f bit in ier0 is set to 1 and the mode mn0 and mode mn1 bits in ifr0 are changed, an interrupt occurs. this interrupt can be used to manage the bulk maximum packet size and descriptor information. 12.5.2 usb cable disconnection if the usb cable enters the disconnection state from the connection state, pe rform the operation as shown in figure 12.3. usb function during usb cable connection usvbus pin = low in full-speed mode: mode mn 0/1 in ifr0 = 01 in high-speed mode: mode mn 0/1 in ifr0 = 10 usb cable disconnection vbus f in ifr0 = 1 vbus mn in ifr0 = 0 mode mn 0/1 in ifr0 = 00 d+ pull-up off mode mn 0/1 in ifr0 = 00 clear interrupt flag (vbus f in ifr0 = 0) write 0 to pullupe bit (pullupe in ctrl = 0) wait for usb cable connection firmware interrupt generated figure 12.3 usb cable disconnection as not shown in figure 12.3, when the mode f bit in ier0 is set to 1 and the mode mn0 and mode mn1 bits in ifr0 are changed, an interrupt occurs.
rev. 2.00, 03/04, page 343 of 534 12.5.3 control transfer the control transfer consists of three stages; setu p, data (sometimes omitted), and status, as shown in figure 12.4. the data stage consists of multiple bus transactions. figures 12.5 to 12.9 show operation flows in each stage. control-in setup stage data stage status stage control-out no data setup(0) data0 setup(0) data0 setup(0) data0 in(1) data1 out(1) data1 in(0) data0 out(0) . . . . . . data0 in(0/1) data0/1 out(0/1) data0/1 out(1) data1 in(1) data1 in(1) data1 figure 12.4 control tr ansfer stage co nfiguration
rev. 2.00, 03/04, page 344 of 534 1. setup stage usb function firmware receive setup token receive 8-byte command data in ep0s to data stage set setup request receive complete flag (setup ts in ifr0 = 1) automatic processing by this module (end) clear interrupt flag (setup ts in ifr0 = 0) clear ep0i fifo (ep0iclr in fclr0 = 1) clear ep0o fifo (ep0oclr in fclr0 = 1) read 8-byte data from ep0s decode command data determine data stage direction * 1 to control-in data stage to control-out data stage command to be processed by firmware? interrupt generated yes no ack notes: 1. in the setup stage, the firmware first analyzes the request data that is sent from the host required to be processed by the firmware, and determines subsequent processing. (for example, the data stage direction.) 2. when the transfer direction is control-out, the ep0i transfer request interrupt that is required in the status stage should be enabled. when the transfer direction is control-in, this interrupt is not required and must be disabled. * 2 figure 12.5 setup stage operation
rev. 2.00, 03/04, page 345 of 534 2. data stage (control-in) the firmware first analyzes the request data that is sent from the host in the setup stage, and determines the subsequent data stage direction. if the result of request data analysis is that the data stage is in-transfer, one packet of data to be sent to the host is written to the fifo. if there is more data to be sent, this data is written to the fifo after the data written first has been sent to the host (ep0i ts bit in ifr0 is set to 1). the end of the data stage is identified when th e host transmits an out token and the status stage is entered. usb function firmware receive in token transmit data to host set ep0i transmit complete flag (ep0i ts in ifr0 = 1) from setup stage write data to ep0i data register (epdr0i) write number of transmit data bytes to packet enable register 0i (pkte0i) clear interrupt flag (ep0i ts in ifr0 = 0) write number of transmit data bytes to packet enable register 0i (pkte0i) every packet. write data to ep0i data register (epdr0i) 0 written to setup ts in ifr0? valid data in ep0i fifo? nak nak no no yes yes ack interrupt generated note: if the size of the data transmitted by the function is smaller than the data size requested by the host, the function indicates the end of the data stage by returning to the host a packet shorter than the maximum packet size. if the size of the data transmitted by the function is an integral multiple of the maximum packet size, the function indicates the end of the data stage by transmitting a zero-length packet. figure 12.6 data stag e operation (control-in)
rev. 2.00, 03/04, page 346 of 534 3. data stage (control-out) the firmware first analyzes the request data that is sent from the host in the setup stage, and determines the subsequent data stage direction. if the result of request data analysis is that the data stage is out-transfer, data from the host is waited for, and after data is received (ep0o ts bit in ifr0 is set to 1), data is read from the fifo. the end of the data stage is identified when the host transmits an in token and the status stage is entered. usb function firmware receive out token receive ping token full speed high speed receive data from host receive ping token (high speed) receive out token (full speed) set ep0o receive complete flag (ep0o ts in ifr0 = 1) clear interrupt flag (ep0ots in ifr0 = 0) confirm receive data length from ep0o receive data size register (epsz0o) read data from ep0o data register (epdr0o) 0 written to setup ts in ifr0? is all received data in fifo read? nak nak ack (for only ping) nyet (high speed) ack (full speed and 0-length packet) ack (for only ping) no yes no yes interrupt generated figure 12.7 data stag e operation (control-out)
rev. 2.00, 03/04, page 347 of 534 4. status stage (control-in) the control-in status stage star ts with an out token from the host. the firmware receives 0- length packet from the host, and ends control transfer. usb function firmware receive out token receive 0-length packet from host end of control transfer set ep0o receive complete flag (ep0o ts in ifr0 = 1) clear interrupt flag (ep0o ts in ifr0 = 0) end of control transfer ack interrupt generated figure 12.8 status stag e operation (control-in)
rev. 2.00, 03/04, page 348 of 534 5. status stage (control-out) the control-out status stage starts with an in token from the host. when an in-token is received at the start of the status stage, there is not yet any data in th e ep0i fifo, and so an ep0i transfer request interrupt is generated. the firmware recognizes from this interrupt that the status stage has started. next, in order to tran smit 0-length packet to the host, 0 is written in the packet enable register 0i but no data is wr itten to the ep0i fifo. as a result, the next in token causes 0-length packet to be transmit ted to the host, and control transfer ends. after the firmware has finished all processing relating to the data stage, 0 should be written in the packet enable register 0i. no ye s no ye s ack nak nak usb function receive in token is setup ts in ifr0 cleared to 0? valid data in ep0i fifo? transmit data to host set ep0i transmit complete flag (ep0i ts in ifr0 = 1) end of control transfer clear interrupt flag (ep0i tr in ifr0 = 0) write 0 to packet enable register 0i (pkte0i) clear interrupt flag (ep0i ts in ifr0 = 0) end of control transfer firmware ep0i transfer request interrupt prohibited (ep0i tr in ier0 = 0) interrupt generated interrupt generated figure 12.9 status stag e operation (control-out)
rev. 2.00, 03/04, page 349 of 534 12.5.4 ep1 bulk-out transfer (dual fifo) ep1 has two 64-byte fifos in full-speed mode and two 512-byte fifos in high-speed mode, but the user can receive data and read receive data without being awar e of this dual-fifo configuration. make sure to confirm that the ep1 full bit in ifr0 is set to 1 before reading the single fifo. when one fifo is full after recep tion is completed, the ep1 full bi t in ifr0 is set. after the first receive operation into one of the fifos when both fifos are em pty, the other fifo is empty, and so the next packet can be received immediat ely. when both fifos are full, nak is returned to the host automatically. when r eading of the receive data is co mpleted following data reception, this operation empties the fifo that has just been read, and makes it ready to receive the next packet. if 0-length packet is received from the host, the ack handshake is returned to the host regardless of mode (full-speed or high-speed mode) and the ep1 full bit in ifr0 is not set. note: the dual-configured fifos are handled in packet units. theref ore, even if either of fifos is empty because of a short packet, when th e packet is received su ccessfully, both fifos become full.
rev. 2.00, 03/04, page 350 of 534 no no no high speed receive out token receive ping token receive data from host full speed usb function firmware ye s ye s no interrupt generated interrupt generated ye s ye s ack (for only ping) nyet (high speed) ack (full speed) nak ack is there any space in ep1 fifo? is receive data length 0? is there any space in other ep1 fifo? set ep1 fifo full status (ep1 full in ifr0 = 1) set ep1 fifo full status (ep1 full in ifr0 = 1) confirm receive data length from ep1 receive data size register (epsz1) read data from ep1 data register (epdr1) is there any space in both ep1 fifos? clear ep1 fifo full status (ep1 full in ifr0 = 0) figure 12.10 ep1 bulk-out transfer operation
rev. 2.00, 03/04, page 351 of 534 12.5.5 ep2 bulk-in transfer (dual fifo) ep2 has two 64-byte fifos in full-speed mode and two 512-byte fifos in high-speed mode, but the user can transmit data and write transmit data without being aware of this dual-fifo configuration. however, one data write should be performed for one fifo. for example, even if both fifos are empty, it is not possible to write the number of transmit data in pkte2 at one time after consecutively writing 128 bytes of data in full-speed mode or 1024 bytes of data in high- speed mode. the number of transmit data must be written in pkte2 for each 64-byte write in full- speed mode or 512-byte write in high-speed mode. make sure to confirm that the ep2empty bit in ifr0 is set to 1 before writing data. when performing bulk-in transfer is required, write 1 to the ep2 empty bit in ier0 first and then enable the ep2 fifo empty interrupt. at first, both ep2 fifos are empty, and so an ep2 fifo empty interrupt is generated immediately. the data to be transmitted is written to the data regi ster using this interrupt. after the first transmit data write for one fifo, the other fifo is empty, and so the next transmit data can be written to the other fifo immediately. when both fifos are full, the ep2 empty bit is cleared to 0. if at least one fifo is empty, the ep2 empty bit in ifr0 is set to 1. when ack is returned from the host after data transmission is completed, the fi fo used in the data transmission becomes empty. if the other fifo contains valid transmit data at this time, transmission can be continued. when transmission of all data has been completed, write 0 to the ep2 empty bit in ier0 and disable interrupt requests. note: the dual-configured fifos are handled in packet units. theref ore, even if either of fifos is empty because of a short packet, when the number of transmit data is written in the packet enable register 2 (pkte2), both fifos become full.
rev. 2.00, 03/04, page 352 of 534 no usb function receive in token interrupt generated valid data in ep2 fifo? transmit data to host is there any space in ep2 fifo? firmware ye s no is there any data to be transmitted to host? ye s nak ack no no ye s ye s clear ep2 empty status (ep2 empty in ifr0 = 0) set ep2 empty status (ep2 empty in ifr0 = 1) enable ep2 fifo empty interrupt (ep2 empty in ier0 = 1) has all data been transmitted to host? write one-packet data to ep2 data register (epdr2) write number of transmit data bytes to packet enable register 2 (epdr2) disable ep2 fifo empty interrupt (ep2 empty in ier0 = 0) figure 12.11 ep2 bulk-in transfer operation
rev. 2.00, 03/04, page 353 of 534 12.5.6 ep3 interrupt-in transfer usb function firmware receive in token transmit data to host set ep3 transmit complete flag (ep3 ts in ifr0 = 1) write data to ep3 data register (epdr3) write number of transmit data bytes to packet enable register 3 (pkte3) clear ep3 transmit complete flag (ep3 ts in ifr0 = 0) write data to ep3 data register (epdr3) write number of transmit data bytes to packet enable register 3 (pkte3) valid data in ep3 fifo? is there any data to be transmitted to host? is there any data to be transmitted to host? no yes no yes no yes nak ack note: this flowchart shows just one example of interrupt-in transfer processing. other possibilities include an operation flow in which, if there is data to be transmitted, the ep3de bit in dasts0 is referred to confirm that the fifo is empty, and then data is written to the fifo. interrupt generated figure 12.12 ep3 interru pt-in transfer operation
rev. 2.00, 03/04, page 354 of 534 12.5.7 processing of usb standard requests and class/vendor requests 1. processing of requests transmitted by control transfer a request transmitted from the host by control transfer may require decoding and execution of request processing by the firmware. whether or not request decoding is required by the firmware is indicated in table 12.2 below. table 12.2 request decoding by firmware decoding not necessary by firmwar e decoding necessary by firmware clear feature get configuration get interface get status set address set configuration set feature set interface get descriptor synch frame set descriptor class/vendor request if decoding is not necessary by the firmware, request decoding and data stage and status stage processing are performed automatically. no processing is necessary by the user. an interrupt is not generated in this case. if decoding is necessary by the firmware, this module stores the request in the ep0s fifo. after normal reception is complete d, the setupts flag in ier0 is set and an interrupt request is generated. in the interrupt routine, eight bytes of data must be read from the ep0s data register (epdr0s) and decoded by the firmware. the necessa ry data stage and status stage processing should then be carried out accordi ng to the result of the decoding operation.
rev. 2.00, 03/04, page 355 of 534 12.5.8 stall operations this section describes stall operations in the usb module. there are two cases in which the usb module stall function is used: ? when the firmware forcibly stalls an endpoint for some reason ? when a stall is performed automatically within the usb module due to a usb specification violation the usb module has internal status bits that hold the status (sta ll or non-stall) of each endpoint. when a transaction is sent from the host, the module refers these internal status bits and determines whether to return a stall to the host. these bits cannot be cleared by the firmware; they must be cleared with a clear feat ure request from the host. however, the internal status bit for ep0 is cleared automatically at th e reception of the setup request. 1. forcible stall by firmware the firmware uses epstl0 to issue a stall re quest for the usb module. when the firmware wishes to stall a specific endpoint, it sets the corresponding bit in epstl0 (1-1 in figure 12.13). the internal status bits are not changed at this time. when a transaction is sent from the host for the endpoint for which the corresponding bit in epstl0 was set, the usb module refers the internal status bit, and if this is not set, refers the corresponding bit in epstl0 (1-2 in figure 12.13). if the corresponding bit in epstl0 is set, the usb module sets the internal status bit and returns a stall handshake to the host (1-3 in figure 12.13). if the corresponding bit in epstl0 is not set, the internal status bit is not changed and the transaction is accepted. once an internal status bit is set, it remains set until cleared by a clear feature request from the host, without regarding to epstl0. even afte r a corresponding bit is cleared by the clear feature request (3-1 in figure 12.13), the usb module continues to return a stall handshake while the bit in epstl0 is set, since the intern al status bit is set each time a transaction is executed for the corresponding endpoint (1-2 in figu re 12.13). to clear a st all, therefore, it is necessary for the corresponding bit in epstl0 to be cleared by the firmware and also for the internal status bit to be cleared with a clear feature request (2-1, 2-2, and 2-3 in figure 12.13).
rev. 2.00, 03/04, page 356 of 534 (1) transition from normal operation to stall (1-1) transaction request usb reference usb function module (1-2) stall handshake stall to (2-1) or (3-1) to (1-3) or (1-4) normal status restored (1-3) (2) when clear feature is sent after epstl0 has been cleared (2-1) stall handshake transaction request (2-2) clear feature command clear feature command (2-3) (3) when clear feature is sent before epstl0 is cleared to 0 (3-1) 1. set epstl0 to 1 by firmware 1. receive in/out token from the host 2. refer to epstl0 1. transmit stall handshake 1. clear internal status bit to 0 1. clear internal status bit to 0 2. no change in epstl0 1. epstl0 is set to 1 2. set internal status bit to 1 3. transmit stall handshake 1. clear epstl0 to 0 by firmware 2. receive in/out token from the host 3. internal status bit has been set to 1 4. epstl0 is not referred to 5. no change in internal status bit to (1-2) internal status bit 0 epstl0 0 1 internal status bit 0 epstl0 1 internal status bit 0 1 epstl0 1 internal status bit 1 epstl0 1 0 internal status bit 1 epstl0 0 internal status bit 1 0 epstl0 0 internal status bit 1 0 epstl0 1 figure 12.13 forcibl e stall by firmware
rev. 2.00, 03/04, page 357 of 534 2. automatic stall by usb function module when a stall setting is made with the set featur e request or in the event of a usb specification violation, the usb module automatically sets the internal status bit for the corresponding endpoint without regarding to epstl0, and returns a stall handshake (1-1 in figure 12.14). once an internal status bit is set, it remains set until cleared by a clear feature request from the host, without regarding to epstl0. after a corresponding bit is cleared by the clear feature request, epstl0 is referred (3-1 in figure 12.14). the usb module continues to return a stall handshake while the internal status bit is set, since the internal status bit is set even if a transaction is executed for the corresponding endpoint (2-1 and 2-2 in figure 12.14). to clear a stall, therefore, the internal status bit must be cleared with a clear feature request (3-1 in figure 12.14). if set by the firmware, epstl0 should also be cleared (2-1 in figure 12.14). (1) transition from normal operation to stall (2) when transaction is performed while internal status bit is set stall handshake transaction request stall handshake (2-2) clear feature command (3) when clear feature is sent before transaction is performed (3-1) 1. in case of usb specification violation, usb function module stalls endpoint automatically. 1. transmit stall handshake 1. clear the internal status bit to 0 2. no change in epstl0 1. clear epstl0 to 0 by firmware 2. receive in/out token from the host 3. internal status bit has been set to 1 4. epstl0 is not referred to 5. no change in internal status bit normal status restored internal status bit 0 1 epstl0 0 internal status bit 1 epstl0 0 internal status bit 1 epstl0 0 internal status bit 1 0 epstl0 0 stall status maintained usb function module to (2-1) or (3-1) (1-1) (2-1) figure 12.14 automatic stall by usb function module
rev. 2.00, 03/04, page 358 of 534 12.5.9 tree configuration this section describes the tree configuration of this module. the usb determines the tree configuration in the function using three parameters such as configuration, interface, and alternate. the tree configuration of this module is shown in table 12.3. table 12.3 tree configuration ep number conf. int. alt. transfer method transfer direction 0 ? ? ? control in/out 1 1 0 0 bulk out 2 1 0 0 bulk in 3 1 0 0 interrupt in 12.5.10 power supply specification this module functions by self power supply. the bus power supply supplied from the usb cable is not available. 12.6 notes on using dma ? pkte2 operation (ep2) when dma transfer is performed on ep2 transmit data, the usb module automatically performs the same processing as writing the number of transmit data to pkte2 if one data fifo (maximum packet size) beco mes full. accordingly, to transf er data of integral multiples of the maximum packet size, the user needs not to write the number of transmit data in pkte2. to transfer data of less than the maximum pack et size, the user must write the number of transmit data in pkte2 using th e dma transfer end interrupt of the dmac. if the user writes the number of transmit data in pkte2 in cases other than the case when data of less than the maximum packet size is transferred, excess tr ansfer occurs and corr ect operation cannot be guaranteed. figure 12.15 shows an example for transmitting 1050 bytes of data from ep1 to the host in high-speed mode. in this case, internal processing as the same as writing the number of transmit data to pkte2 is automatically performed twice. this kind of internal processing is performed when the currently selected data fifo becomes full. accordingly, this processing is automatically performed only when the maximu m packet size of data is transmitted. this processing is not performed automatically when data less than the maximum packet size is transmitted.
rev. 2.00, 03/04, page 359 of 534 in this example, when the first 512 bytes of data has not been transmitted to the host at the end of dma transfer on the first 512 bytes of data and second 512 bytes of data, the dma request does not occur. if the transmission has been completed, the dma request occurs because there is space in the one fifo. when the last 26 bytes of data has been transferred, there is no data to be transferred in the firmware. however, the dma request occurs if there is space in the fifo. therefore, when dma transfer is completed on all data, the dma enable state should be cl eared by writing 0 to the ep2dmae bit in dma0. note that over-sampling should not be performed by the dmac. generally the number of transmit data is set as the number of dmac tr ansfers and the number of data less than the maximum packet size is written in pkte2 using the dma transfer end interrupt. if the number of tran smit data is an integral multiple of the maximum packet size (for example, 1024 bytes or 2048 bytes), the nu mber of transmit data is automatically written in pkte2. in this case, the user must not write the number of transmit data in pkte2 using the dma transfer end inte rrupt. if the writing is performed, correct operation cannot be guaranteed. 512 bytes 512 bytes 26 bytes pkte2 (automatically performed) pkte2 (automatically performed) pkte2 is not performed executed by dma transfer end interrupt (user) figure 12.15 pkte2 operation for ep2 12.7 transition to usb suspend mode 12.7.1 suspend signal output if the usb continues to be idle for the specified time, the usb enters the suspend state. when the usb enters the suspend state, the ussusp signal is asserted to low and the suspend state can be notified to the external transceiver. when the external transceiver receives the ussusp signal, the clock oscillation is stopped and the power-down state is entered. therefore the usclk supplied to this lsi is stopped. to operate the usb module, the usclk supplied by the ex ternal transceiver and system clock ( ) should be supplied. while the usclk is stopped, programmi ng is required so that access to the usb module does not occur.
rev. 2.00, 03/04, page 360 of 534 to control this, the usb suspend interrupt (usbi2) which notifies that the usb module enters or recovers the suspend state to the cpu and a re gister bit (ususout bit in usbsusp) which controls the external ussusp output are provided. figure 12.16 shows the enter/recover sequence of suspend mode. and the following 1 to 6 descriptions explain the operation at its each point. usclk internal suspend signal usbi2 interrupt request initial setting : signal mask period interrupt flag cleared [2] [3] [4] [5] [6] [1] mask signal figure 12.16 enter/recover sequence of usb suspend state 1. usbsusp output mask when the ususout bit in usbsusp is cleared to 0, output of the ussusp pin is masked (fixed to 1) and notification of the suspend state to the external transceiver is disabled. 2. entering suspend state by usb module if the usb continues to be idle for the specifi ed time, the usb module asserts the internal suspend signal and enters th e suspend state. since the ussusp output is masked by means of the ususout bit in usbsusp, the external pin, ussusp , is not changed. 3. usb suspend interrupt (usbi2) when the ususfge bit in usbsusp is set to 1 and the internal suspend signal of the usb module is changed, an interrupt (usbi2) can be requested to the cpu. as the initial setting, the ususfg bit (interrupt flag) in usbsusp should be cleared to 0 and then the ususfge bit in usbsusp should be set to 1. the usbi2 interrupt request occurs when the in ternal suspend signal of the usb module is changed. after the interrupt flag is cleared in the interrupt routine, monitor the ususmoni bit in usbsusp and confirm that the interrupt occurs because of transition to the suspend state. note that an interrupt occurs when transition is made in the following order: normal mode, suspend mode, and normal mode.
rev. 2.00, 03/04, page 361 of 534 4. clearing suspend signal output mask to prevent access to the usb module by the cpu or dmac from occurring in the interrupt processing routine, the ususout bit in usbsusp is set to 1 after the setting such as to stop the dmac is made. then output of the ussusp pin goes low and the usclk input from the external transceiver is stopped. after the usclk input is stopped, do not ac cess the usb module registers by the cpu or dmac. 5. usb suspend interrupt (usbi2) even if the usclk is stopped, the internal susp end signal is negated after the usb bus state is recovered from the suspend state. since the usbi2 interrupt is requested when the internal suspend signal is changed, if interrupts are enabled, an interrupt is requested to the cpu even when the internal suspend signal is negated. 6. suspend signal output mask in the interrupt processing routine, output of the ussusp pin should be masked (fixed to 1) by clearing the ususout bit in usbsusp to 0. then access to the usb module registers can be performed by the cpu or dmac. 12.7.2 software standby in suspend mode in the firmware mainly for the usb, if the usb enters suspend mode, this lsi enters software standby mode which is the power-down state because power consumption of the system can be reduced. since the system clock ( ) is stopped in software standby mode, the suspend recover interrupt (susri) is used to rec over from software standby mode. figure 12.17 shows the enter/recover sequence of suspend mode and software standby mode. and the following 1 to 8 descriptions ex plain the operation at its each point.
rev. 2.00, 03/04, page 362 of 534 usclk internal suspend signal usbi2 interrupt request mask signal susri interrupt request initial setting : signal mask period. during the period other than the signal mask period, the internal suspend signal is inverted and output. [1] [2] [3] [4] [5] [6] [7] [8] interrupt flag cleared interrupt flag cleared interrupt flag cleared software standby mode oscillation stabilization time figure 12.17 enter/recover sequence of us b suspend state and software standby mode 1. ussusp output mask when the ususout bit in usbsusp is cleared to 0, output of the ussusp pin is masked (fixed to 1) and notification of the suspend state to the external transceiver is disabled. 2. entering suspend state by usb module if the usb continues to be idle for the specifi ed time, the usb module asserts the internal suspend signal and enters th e suspend state. since the ussusp output is masked by means of the ususout bit in usbsusp, the external pin, ussusp , is not changed. 3. usb suspend interrupt (usbi2) when the ususfge bit in usbsusp is set to 1 and the internal suspend signal of the usb module is changed, an interrupt (usbi2) can be requested to the cpu. as the initial setting, the ususfg bit (interrupt flag) in usbsusp should be cleared to 0 and then the ususfge bit in usbsusp should be set to 1. the usbi2 interrupt request occurs when the in ternal suspend signal of the usb module is changed. after the interrupt flag is cleared in the interrupt routine, monitor the ususmoni bit in usbsusp and confirm that the interrupt occurs because of transition to the suspend state. note that an interrupt occurs when transition is made in the following order: normal mode, suspend mode, and normal mode.
rev. 2.00, 03/04, page 363 of 534 4. clearing suspend signal output mask to prevent access to the usb module by the cpu or dmac from occurring in the interrupt processing routine, the ususout bit in usbsusp is set to 1 after the setting such as to stop the dmac is made. then output of the ussusp pin goes low and the usclk input from the external transceiver is stopped. after the usclk input is stopped, do not access the usb module registers by the cpu or dmac. 5. entering software standby mode when the usb bus state enters the state other th an the usb idle state before software standby mode is entered, the suspend recover interrupt (s usri) is set in order to clear software standby mode. to enable the suspend recover interrupt (susri), clear the susrif bit in pfcr3 to 0 and then set the susrie bit in pfcr3 to 1. after that, the sleep instruction is executed while the ssby bit in sbycr is set to 1 in order to enter software standby mode. the system clock ( ) is stopped and this lsi enters the power-down state. 6. recover event from suspend if the usb bus state recovers from the suspend state, the suspend recover interrupt (susri) is requested. by this interrupt request, software standby mode can be cancelled. if the usb bus state recovers from the suspend state, the ussusp pin is negated and this lsi starts oscillation. after the specified oscillatio n stabilization time is elapsed, the internal system clock is supplied and the cpu execut es the suspend recover interrupt (susri) processing. 7. suspend recover interrupt (susri) in the interrupt processing rou tine, clear the susrif bit in pfcr3 to 0 and then clear the susrie bit in pfcr3 to 0 in order to disable the suspend recover interrupt (susri). at this time, the usbi2 interrupt is requested. the priority of the susri interrupt must be higher than that of the usbi2 interrupt. 8. usb suspend interrupt (usbi2) after recovering from the susri interrupt processing, the pending usbi2 interrupt processing is executed. to mask output of the ussusp pin (fix to 1), clear the ususout bit in usbsusp to 0 in the interrupt processing routine. then access to the usb registers can be performed by the cpu or dmac.
rev. 2.00, 03/04, page 364 of 534 12.8 usage notes 12.8.1 setup da ta reception the following must be noted for the ep0s fifo used to receive 8-byte setup data. the usb is designed to always r eceive setup requests. accordingl y, write from the usb bus has higher priority than read from cpu. if the recep tion of the next setup request starts while cpu is reading data after completing reception, this data re ad from cpu is forcibly cancelled and the next setup request write starts. after the next setu p request write, data read from cpu is thus undefined. 12.8.2 fifo clear if the usb cable is disconnected during communication, old data may be contained in the fifo. accordingly, fifos must be cleared immediately afte r usb cable connection. note, however, that fifos th at are currently used for data transfer to or from the host must not be cleared. 12.8.3 operating frequency the system clock ( ) must range from 31 mhz to 33 mhz. 12.8.4 interrupts this module uses signals in which each bit in if r0 is logical-ored as interrupt requests. thus, even if a flag is cleared, the request is not ne gated while at least one of other flags is set. 12.8.5 register access size in this module, all registers should be accessed in 32-bit units using the mov.l instruction. they cannot be accessed in 8- or 16-b it units using instructions such as mov.w, mov.b, or bit manipulation instruction.
rev. 2.00, 03/04, page 365 of 534 12.8.6 data register overread or overwrite when data registers in this module are read fro m or written to, the following must be noted: 1. receive data register receive data registers must not read a data size th at is greater than the effective size of the read data item. in other words, receive data registers must not read data with data size larger than that specified by the receive data size register . for the receive data re gister of ep1 having a dual-fifo configuration, data to be read at an y time must be within the maximum packet size. make sure to confirm that the ep1 full bit in ifr0 is set to 1 before reading from data from a single fifo, because data registers ca nnot be accessed while fifos are switched. 2. transmit data register data to be written to the transmit data registers must be within the maximum packet size. for the transmit data register of ep2 having a dual-fifo configuration, data to be written at any time must be within the maximum packet size. in this case, after a data write, the fifo is switched to the other fifo, enabling an further data write, when the number of transmit data is written in pkte2. accordingly, data of size corresponding to two fifos must not be written to the transmit data registers at a time. make sure to confirm that the ep2empty bit in ifr0 is set to 1 before writing data to a single fifo , because data registers cannot be accessed while fifos are switched. 12.8.7 ep0 interrupt sources assignment ep0 interrupt sources assigned to bits 3 to 0 in if r0 must be assigned to the same interrupt signal by setting isr0. there are no other restrictions on interrupt sources. 12.8.8 fifo size at full speed mode this module operates in high-spee d or full-speed mode. the fifo si ze to be used in each mode is shown below. therefore, data more than 64 bytes cannot be read from or written to the one fifo for ep1 or ep2 in full-speed mode. if the read or wr ite is performed, correct transfer is impossible. data less than 64 bytes should be read from or written to.
rev. 2.00, 03/04, page 366 of 534 table 12.4 fifo size in each transfer mode fifo size endpoint full speed high speed fifo configuration transfer method transfer direction ep0s 8 bytes 8 bytes single setup out ep0i 64 bytes 64 bytes single control in ep0o 64 bytes 64 bytes single control out ep1 64 bytes 512 bytes dual bulk out ep2 64 bytes 512 bytes dual bulk in ep3 64 bytes 64 bytes single interrupt in 12.8.9 level shifter for vbus pin the usvbus pin of this lsi must be connected to the usb connector's vbus pin via a level shifter. (make sure the polarity is correct.) this is because the usb module has a circuit that operates by detecting usb cable connection or disconnection. even if the power of the device incorporating this module is turned off, 5-v power is applied to the usb connector's vbus pin while the usb cable is connected to the device set. to protect the lsi from destruction, use an external level shifte r which allows voltage application to the pin even when the power is off. 12.8.10 usb 2.0 transcei ver (physical layer) this module does not include the usb 2.0 transceiver. therefore an external transceiver should be used. 12.8.11 epdr0s read epdr0s must be read in 8-byte units. otherwise, the data receive d in the next setup cannot be read normally. 12.8.12 usb bus idle in high-speed mode when the usb bus enters the idle state in high-speed mode, this module enters full-speed mode. however, the mode mn1 and mode mn0 bits in ifr0 are not changed. therefore, the modef bit in ifr0 is not set.
rev. 2.00, 03/04, page 367 of 534 12.8.13 note on usb bus disconnection if the connector is disconnected by the user rega rdless of whether communication is in progress with the host or the idle state is entered, the usb cable may be disconnected. when the usb cable is disconnected and data transfer is performed between the usb module an d the host, the correct transfer cannot be performed after the cable is connected again. therefore, when the cable disconnection is detected, the usb module must be reset. to reset this, set the usbswrst bit in pfcr3 to 1. the cpu must access pfcr3. after the usbswrst bit is set to 1 and one clock is elapsed, clear the usbswrst bit to 0. then, th e usb module operates normally. after a reset, values of all registers in the usb module are returned to the initial values so they should be set again. 12.8.14 example of external circuit since this lsi does not contain the on-chip usb physical layer, the physical layer lsi in the utmi specification should be connected externally. figure 12.19 shows a connection example of the external circuit. figure 12.1 9 is only an example. the actual connecting diff ers according to the specifications of the external physical layer lsi in the utmi specification. usxcvrs ustsel usclk usrxact usrxv usrxerr ustxv ustxrdy usd15 to usd0 uswdvld ussusp uslsta1, uslsta0 usopm1 usopm0 dp dm xcvrselect termselect clk rxactive rxvalid (rxvalidh) rxerror txvalid (txvalidh) txready data15 to data0 validh suspendm linestate [1:0] opmode [1] opmode [0] rst (assert h) vbus (5 v) (3.3 v) usvbus res reset signal power-supply voltage can be applied to this ic even when the system (lsi) power is off. level shifter this lsi external physical layer lsi in the utmi specification usb connector figure 12.18 connection ex ample of external circuit
rev. 2.00, 03/04, page 368 of 534 12.8.15 external physical layer lsi the pin name, usage, and type may differ according to each of external physical layer lsi. check and confirm the specifications of it before connecting to this lsi. 12.8.16 operation at the bus reset reception when a bus reset is received from the host, there will be a defect in the operation described below. when the first bus reset from the host completes, and then the second bus reset is received without following bus accesses of sof or data transfer , the second bus reset will not be received successfully (shown in cas e 2 in figure 12.19). bus reset (first) sof, etc. bus reset (first) case 1 case 2 no transfer (idle) bus reset (second) bus reset (second) figure 12.19 bus reset following completion of first bus reset note: since the successive bus resets are not normally required, the bus reset does not occur successively with following no data transfer. in order to detect the bus reset correctly, even in the case 2, follow the pr ocedure shown in figure 12.20.
rev. 2.00, 03/04, page 369 of 534 ifr0/setup ts=1? usbsusp/ususfg=1? ifr0/vbus f=1? no no ye s ye s ye s normal bus reset processing clear usbsusp/ususfg flag to 0 pfcr3/usbswrst 1 write pfcr3/usbswrst 0 write usb module initial setting (isr0/ier0 etc) ctrl/pullupe 1 write end figure 12.20 bus reset detection flow 12.8.17 usage notes in control in transfer in the status stage of the control in tran sfer, 0-length packet is only received. 12.8.18 usb interrupt during software standby as the usb clock stops during software standby, usbi0 and usbi1 interrupts like vbus interrupt will not be generated.
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rev. 2.00, 03/04, page 371 of 534 section 13 ram this lsi has an on-chip high-speed static ram. the ram is connected to the cpu by a 16-bit data bus and is connected to the dmac by a 32 -bit data bus, enabling one-state access to byte data, word data, and longword data (note that tw o-state access is used when the ram is accessed by using the longword access instruc tion such as mov.l by the cpu). the on-chip ram can be enabled or disabled by means of the rame bit in the system control register (syscr). for details on the system c ontrol register (syscr), refer to section 3.2.2, system control register (syscr). product type rom type ram capacity ram address h8s/2170 HD64F2170 flash memory vers ion 32 kbytes h'ff7000 to h'ffefff
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rev. 2.00, 03/04, page 373 of 534 section 14 flash memory (0.18- m f-ztat version) the flash memory has the follow ing features. figure 14.1 shows a block diagram of the flash memory. 14.1 features ? size product classification rom size rom address h8s/2170 HD64F2170 256 kb ytes h'000000 to h'03ffff ? two flash-memory ma ts according to lsi initiation mode the on-chip flash memory has two memory sp aces in the same address space (hereafter referred to as memory mats). the mode setting in the initiation determines which memory mat is initiated first. the mat can be switched by using the bank-switching method after initiation. ? the user memory mat is initiated at a power-on reset in user mode: 256 kbytes ? the user boot memory mat is initiated at a power-on reset in user boot mode: 8 kbytes ? programming/erasing interface by the download of on-chip program this lsi has a dedicated programming/erasing program. after downloading this program to the on-chip ram, programming/erasing can be performed by setting the argument parameter. ? programming/erasing time the flash memory programming time is 3 ms (typ) in 128-byte simultaneous programming and approximately 25 s per byte. the erasing time is 1000 ms (typ) per 64-kbyte block. ? number of programming the number of flash memory programming can be up to 100 times at the minimum. (the value ranged from 1 to 100 is guaranteed.) ? three on-board programming modes ? boot mode this mode is a program mode that uses an on-chip sci inte rface. the user mat and user boot mat can be programmed. this mode can automatically adjust the bit rate between host and this lsi. ? user program mode the user mat can be programmed by using the optional interface. ? user boot mode the user boot program of the optional inte rface can be made and the user mat can be programmed.
rev. 2.00, 03/04, page 374 of 534 ? programming/erasing protection sets protection against flash memory programming/erasing via hardware, software, or error protection. ? programmer mode this mode uses the prom programmer. the user mat and user boot mat can be programmed. fccs fpcs fecs fkey fmats control unit memory mat unit flash memory user mat: 256 kbytes user boot mat: 8 kbytes operating mode module bus fwe pin mode pin internal address bus internal data bus (16 bits) legend fccs: flash code control status register fpcs: flash program code select register fecs: flash erase code select register fkey: flash key code register fmats: flash mat select register ftdar: flash transfer destination address register ftdar figure 14.1 block diagram of flash memory
rev. 2.00, 03/04, page 375 of 534 14.1.1 operating mode when each mode pin and the fwe pin are set in the reset state and reset start is performed, this lsi enters each operating mode as shown in figure 14.2. ? flash memory can be read in user mode, but cannot be programmed or erased. ? flash memory can be read, programmed, or eras ed on the board only in user program mode, user boot mode, and boot mode. ? flash memory can be read, programmed, or er ased by means of the prom programmer in programmer mode. reset state programmer mode user mode user program mode user boot mode boot mode on-board programming mode = 0 = 0 user mode setting user boot mode setting = 0 boot mode setting = 0 = 0 programmer mode setting fwe = 0 fwe = 1 figure 14.2 mode transition of flash memory
rev. 2.00, 03/04, page 376 of 534 14.1.2 mode comparison the comparison table of programming and erasing related items about boot mode, user program mode, user boot mode, and programmer mode is shown in table 14.1. table 14.1 comparison of programming modes boot mode user program mode user boot mode programmer mode programming/ erasing environment on-board on-board on-board prom programmer programming/ erasing enable mat user mat user boot mat user mat user mat user mat user boot mat all erasure (automatic) (automatic) block division erasure * 1 program data transfer from host via sci from optional device via ram from optional device via ram via programmer reset initiation mat embedded program storage mat user mat user boot mat * 2 ? transition to user mode changing mode setting and reset changing flshe bit and fwe pin changing mode setting and reset ? notes: 1. all-erasure is performed. afte r that, the specified block can be erased. 2. firstly, the reset vector is fetched fr om the embedded program storage mat. after the flash memory related registers are checked, the reset vector is fetched from the user boot mat. ? the user boot mat can be programmed or erased only in boot mode and programmer mode. ? the user mat and user boot mat are erased in boot mode. then, the user mat and user boot mat can be programmed by means of the command method. however, the contents of the mat cannot be read until this state. ? there are some possible ways in this mode such as, writing only to the user boot mat while rewriting the user mat in user boot mode, or rewriting only the user mat due to not using the user boot mode. the boot operation of the optional interface can be performed by the mode pin setting different from user program mode in user boot mode.
rev. 2.00, 03/04, page 377 of 534 14.1.3 flash mat configuration this lsi's flash memory is configured by the 256-kbyte user mat and 8-kbyte user boot mat. the start address is allocated to the same address in the user mat and user boot mat. therefore, when the program execution or data access is performed between two mats, the mat must be switched by using fmats. the user mat or user boot mat can be read in all modes. however, the user boot mat can be programmed only in boot mode and programmer mode. address h'000000 address h'03ffff address h'000000 address h'001fff 256 kbytes 8 kbytes figure 14.3 flash memory configuration the size of the user mat is different from that of the user boot mat. an address which exceeds the size of the 8-kbyte user boot mat should not be accessed. if the attempt is made, data is read as undefined value.
rev. 2.00, 03/04, page 378 of 534 14.1.4 block division the user mat is divided into 64 kbytes (three blocks), 32 kbytes (one block), and 4 kbytes (eight blocks) as shown in figure 14.4. the user mat can be erased in this divided-block units and the erase-block number of eb0 to eb11 is specified when erasing. eb0 erase unit: 4 kbytes eb1 erase unit: 4 kbytes eb2 erase unit: 4 kbytes eb3 erase unit: 4 kbytes eb4 erase unit: 32 kbytes eb5 erase unit: 4 kbytes eb6 erase unit: 4 kbytes eb7 erase unit: 4 kbytes eb8 erase unit: 4 kbytes eb9 erase unit: 64 kbytes h'000000 h'000001 h'000002 h'00007f h'000fff h'00107f h'00207f h'00307f h'00407f h'00bfff h'00c07f h'00cfff h'001fff h'002fff h'003fff h'01ffff h'00d07f h'00dfff h'00e07f h'00efff h'00f07f h'00ffff h'01007f ? programming unit: 128 bytes ? programming unit: 128 bytes ? programming unit: 128 bytes ? programming unit: 128 bytes ? programming unit: 128 bytes ? programming unit: 128 bytes ? programming unit: 128 bytes ? programming unit: 128 bytes ? programming unit: 128 bytes ? programming unit: 128 bytes h'001000 h'001001 h'001002 h'002000 h'002001 h'002002 h'003000 h'003001 h'003002 h'004000 h'004001 h'004002 h'00c000 h'00c001 h'00c002 h'00d000 h'00d001 h'00d002 h'00e000 h'00e001 h'00e002 h'00f000 h'00f001 h'00f002 h'010000 h'010001 h'010002 h'000f80 h'000f81 h'000f82 h'001f80 h'001f81 h'001f82 h'002f80 h'002f81 h'002f82 h'003f80 h'003f81 h'003f82 h'00bf80 h'00bf81 h'00bf82 h'00ff80 h'00ff81 h'00ff82 h'01ff80 h'01ff81 h'01ff82 h'00cf80 h'00cf81 h'00cf82 h'00df80 h'00df81 h'00df82 h'00ef80 h'00ef81 h'00ef82 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? eb10 erase unit: 64 kbytes eb11 erase unit: 64 kbytes h'03ffff h'02007f h'02ffff h'03007f ? programming unit: 128 bytes ? programming unit: 128 bytes h'020000 h'020001 h'020002 h'030000 h'030001 h'030002 h'02ff80 h'02ff81 h'02ff82 h'03ff80 h'03ff81 h'03ff82 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? figure 14.4 block division of user mat
rev. 2.00, 03/04, page 379 of 534 14.1.5 programming/erasing interface programming/erasing is executed by downloading the on-chip program to the on-chip ram and specifying the program address/data and erase bl ock by using the interface register/parameter. the procedure program is made by the user in user program mode and user boot mode. an overview of the procedure is given as follows. for details, see section 14.4.2, user program mode. initialization execution (downloaded program execution) select on-chip program to be downloaded and specify the destination. start user procedure program for programming/erasing. end user procedure program yes programming (in 128-byte units) or erasing (in one-block units) (downloaded program execution) download on-chip program by setting fkey and sco bits. no programming/erasing completed? figure 14.5 overview of user procedure program 1. selection of on-chip program to be downloaded for programming/erasing execution, the fwe pin must be set to 1 to transition to user program mode. this lsi has programming/erasing programs which can be downloaded to the on-chip ram. the on-chip program to be downloaded is selected by setting the corresponding bits in the programming/erasing interface register. the address of the programming destination is specified by the flash transfer des tination address register (ftdar).
rev. 2.00, 03/04, page 380 of 534 2. download of on-chip program the on-chip program is automatically downloaded by setting the flash key register (fkey) and the sco bit in the flash control register (fccs), which are progra mming/erasing interface registers. the flash memory is replaced to the embedded program storage area when downloading. since the flash memory cannot be r ead when programming/erasing, the procedure program, which is working from download to completion of programming/erasing, must be executed in the space other than the flash memory to be programmed/erased (for example, on-chip ram). since the result of download is returned to the programming/erasing interface parameter, whether the normal download is executed or not can be confirmed. 3. initialization of programming/erasing the operating frequency is set before execution of programming/erasing. this setting is performed by using the programmi ng/erasing interface parameter. 4. programming/erasing execution for programming/erasing execution, the fwe pin must be set to 1 to transition to user program mode. the program data/programming destination ad dress is specified in 128-byte units when programming. the block to be erased is specified in erase-block units when erasing. these specifications are set by using the prog ramming/erasing interface parameter and the on- chip program is initiated. the on-chip progr am is executed by using the jsr or bsr instruction and performing the subroutine call of the specified address in the on-chip ram. the execution result is returned to th e programming/erasing interface parameter. the area to be programmed must be erased in advance when programming flash memory. all interrupts are prohibited during programming and erasing. interrupts must be masked within the user system. 5. when programming/erasin g is executed consecutively when the processing is not ended by the 128-byte programming or one-block erasure, the program address/data and erase-block number must be updated and consecutive programming/erasing is required. since the downloaded on-chip program is left in the on-chip ram after the processing, download and initialization are not required when the same processing is executed consecutively.
rev. 2.00, 03/04, page 381 of 534 14.2 input/output pins table 14.2 shows the flash memory pin configuration. table 14.2 pin configuration pin name input/output function res input reset fwe input flash memory programming/erasing enable pin md2 input sets operating mode of this lsi md1 input sets operating mode of this lsi txd0 output serial transmit data output (used in boot mode) rxd0 input serial receive data input (used in boot mode) 14.3 register descriptions the registers/parameters which control flash memory are shown in the following. ? flash code control status register (fccs) ? flash program code sel ect register (fpcs) ? flash erase code select register (fecs) ? flash key code register (fkey) ? flash mat select register (fmats) ? flash transfer destination address register (ftdar) ? ram emulation register (ramer) ? download pass and fail result (dpfr) ? flash pass and fail result (fpfr) ? flash multipurpose address area (fmpar) ? flash multipurpose data destination area (fmpdr) ? flash erase block select (febs) ? flash program and erase frequency control (fpefeq) there are several operating modes for accessing fl ash memory, for example, read mode/program mode. there are two memory mats: user mat and user boot mat. the dedicated registers/parameters are allocated for each operating mode and mat se lection. the correspondence of operating modes and registers/parameters for use is shown in table 14.3.
rev. 2.00, 03/04, page 382 of 534 table 14.3 register/para meter and target mode download initialization program- ming erasure read fccs ? ? ? ? fpcs ? ? ? ? fecs ? ? ? ? fkey ? ? fmats ? ? * 1 * 1 * 2 programming/ erasing interface register ftdar ? ? ? ? dpfr ? ? ? ? fpfr ? ? fpefeq ? ? ? ? fubra ? ? ? ? fmpar ? ? ? ? fmpdr ? ? ? ? programming/ erasing interface parameter febs ? ? ? ? notes: 1. the setting is required when programmi ng or erasing user mat in user boot mode. 2. the setting may be required according to the combination of initiation mode and read target mat. 14.3.1 programming/erasing interface register the programming/erasing interface re gisters are as described below. they are all 8-bit registers that can be accessed in byte. these registers are in itialized at a reset or in hardware standby mode. ? flash code control and status register (fccs) fccs is configured by bits wh ich request the monitor of the fw e pin state and error occurrence during programming or erasing flash memory and the download of on-chip program. bit bit name initial value r/w description 7 fwe 1/0 r flash program enable monitors the signal level input to the fwe pin. 0: a low level signal is input to the fwe pin. (hardware protection state) 1: a high level signal is input to the fwe pin. 6, 5 ? all 0 r/w reserved the initial value should not be changed.
rev. 2.00, 03/04, page 383 of 534 bit bit name initial value r/w description 4 fler 0 r flash memory error indicates an error occurs during programming and erasing flash memory. when fler is set to 1, flash memory enters the error protection state. when fler is set to 1, high voltage is applied to the internal flash memory. to reduce the damage to flash memory, the reset must be released afte r the reset period of 100 s which is longer than normal. 0: flash memory operates normally. programming/erasing protection for flash memory (error protection) is invalid. [clearing condition] ? at a reset or in hardware standby mode 1: an error occurs during programming/erasing flash memory. programming/erasing protection for flash memory (error protection) is valid. [setting conditions] ? when an interrupt, such as nmi, occurs during programming/erasing flash memory. ? when the flash memory is read during programming/erasing flash memory (including a vector read or an instruction fetch). ? when the sleep instruction is executed during programming/erasing flash memory (including software-standby mode) ? when a bus master other than the cpu, such as the dmac, gets bus mastership during programming/erasing flash memory.
rev. 2.00, 03/04, page 384 of 534 bit bit name initial value r/w description 3 weinte 0 r/w program/erase enable modifies the space for the interrupt vector table, when interrupt vector data is not read successfully during programming/erasing flash memory or switching between a user mat and a user boot mat. when this bit is set to 1, interrupt vector data is read from address spaces h'ff8000 to h'ff807f (on-chip ram space), instead of from address sp aces h'000000 to h'00017f (up to vector number 31). therefore, make sure to set the vector table in the on-ch ip ram space before setting this bit to 1. the interrupt exception handling on and after vector number 32 should not be used because the correct vector is not read, resulting in the cpu runaway. 0: the space for the interru pt vector table is not modified. when interrupt vector data is not read successfully, the operation for the interrupt exception handling cannot be guaranteed. an occurrence of any interrupts should be masked. 1: the space for the interrupt vector table is modified. even when interrupt vector data is not read successfully, the interrupt exception handling up to vector number 31 is enabled. 2, 1 ? all 0 r/w reserved the initial value should not be changed.
rev. 2.00, 03/04, page 385 of 534 bit bit name initial value r/w description 0 sco 0 (r)/w * source program copy operation requests the on-chip programming/erasing program to be downloaded to the on-chip ram. when this bit is set to 1, the on-chip program which is selected by fpcs/fecs is automatically downloaded in the on-chip ram specified by ftdar. in order to set this bit to 1, h'a5 must be written to fkey and this operation must be executed in the on-chip ram. four nop instructions must be executed immediately after setting this bit to 1. since this bit is cleared to 0 when download is completed, this bit cannot be read as 1. all interrupts must be disabled. this should be made in the user system. 0:download of the on-chip programming/erasing program to the on-chip ram is not executed. [clearing condition] when download is completed 1: request that the on-chip programming/erasing program is downloaded to the on-chip ram is occurred. [setting conditions] when all of the following conditions are satisfied and 1 is set to this bit ? h'a5 is written to fkey ? during execution in the on-chip ram note: * this bit is a write only bit. this bit is always read as 0.
rev. 2.00, 03/04, page 386 of 534 ? flash program code select register (fpcs) fpcs selects the on-chip programming program to be downloaded. bit bit name initial value r/w description 7 to 1 ? all 0 r/w reserved the initial value should not be changed. 0 ppvs 0 r/w program pulse verify selects the programming program. 0: on-chip programming program is not selected. [clearing condition] when transfer is completed 1: on-chip programming program is selected. ? flash erase code select register (fecs) fecs selects download of the on-chip erasing program. bit bit name initial value r/w description 7 to 1 ? all 0 r/w reserved the initial value should not be changed. 0 epvb 0 r/w erase pulse verify block selects the erasing program. 0: on-chip erasing program is not selected. [clearing condition] when transfer is completed 1: on-chip erasing program is selected.
rev. 2.00, 03/04, page 387 of 534 ? flash key code register (fkey) fkey is a register for software protection that enables download of on-chip program and programming/erasing of flash memory. before setting the sco bit to 1 in order to download on- chip program or executing the downloaded programming/erasing program, these processing cannot be executed if the key code is not written. bit bit name initial value r/w description 7 6 5 4 3 2 1 0 k7 k6 k5 k4 k3 k2 k1 k0 0 0 0 0 0 0 0 0 r/w r/w r/w r/w r/w r/w r/w r/w key code only when h'a5 is written, wr iting to the sco bit is valid. when the value other than h' a5 is written to fkey, 1 cannot be set to the sco bit. therefore downloading to the on-chip ram cannot be executed. only when h'5a is written, programming/erasing can be executed. even if the on-chip programming/erasing program is executed, the flash memory cannot be programmed or erased when t he value other than h'5a is written to fkey. h'a5: writing to the sco bit is enabled. (the sco bit cannot be set by the value other than h'a5.) h'5a: programming/erasing is enabled. (the value other than h'a5 is in softw are protection state.) h'00: initial value
rev. 2.00, 03/04, page 388 of 534 ? flash mat select register (fmats) fmats specifies whether user mat or user boot mat is selected. bit bit name initial value r/w description 7 6 5 4 3 2 1 0 ms7 ms6 ms5 ms4 ms3 ms2 ms1 ms0 0/1 * 0 0/1 * 0 0/1 * 0 0/1 * 0 r/w r/w r/w r/w r/w r/w r/w r/w mat select these bits are in user-ma t selection state when the value other than h'aa is written and in user-boot-mat selection state when h'aa is written. the mat is switched by writ ing the value in fmats. when the mat is switched, follow section 14.6, switching between user mat and user boot mat. (the user boot mat cannot be programmed in user program mode if user boot mat is se lected by fmats. the user boot mat must be programmed in boot mode or in programmer mode.) h'aa: the user boot mat is selected (in user-mat selection state when the value of these bits are other than h'aa) initial value when these bits are initiated in user boot mode. h'00: initial value when these bits are initiated in a mode except for user boot mode (in user-mat selection state) [programmable condition] these bits are in the exec ution state in the on-chip ram. note: * set to 1 when in user boot mode, otherwise set to 0.
rev. 2.00, 03/04, page 389 of 534 ? flash transfer destination address register (ftdar) ftdar specifies the on-chip ram address wher e an on-chip program is downloaded. this register must be specified before setting the sco bit in fccs to 1. bit bit name initial value r/w description 7 tder 0 r/w transfer destination address setting error this bit is set to 1 when the address specified by bits tda6 to tda0, which is the start address where an on- chip program is downloaded, is over the range. whether or not the address specified by bits tda6 to tda0 is within the range of h'00 to h'03 is determined when an on-chip program is downloaded by setting the sco bit in fccs to 1. make sure that this bit is cleared to 0 and the value specified by bits tda6 to tda0 is within the range of h'00 to h'03 before setting the sco bit to 1. 0: the value specified by bits tda6 to tda0 is within the range. 1: the value specified by bits tda6 to tda0 is over the range (h'04 to h'ff) and download is stopped. 6 5 4 3 2 1 0 tda6 tda5 tda4 tda3 tda2 tda1 tda0 0 0 0 0 0 0 0 r/w r/w r/w r/w r/w r/w r/w transfer destination address specifies the start address wh ere an on-chip program is downloaded. a value from h'00 to h'03 can be specified as the download start address in the on-chip ram. h'00: h'ff7000 is specifi ed as the download start address. h'01: h'ffb000 is specified as the download start address. h'02: h'ffd000 is specified as the download start address. h'03: h'ffe800 is specified as the download start address. h'04 to h'ff: setting prohibit ed. specifying this value sets the tdre bit to 1 during downloading and stops the download.
rev. 2.00, 03/04, page 390 of 534 ? ram emulation register (ramer) ramer specifies the area of flash memory to be overlapped with part of ram when emulating realtime flash memory programming. ramer is initialized to h'00 by a power-on reset and in hardware standby mode. it is not initialized in software standby mode. ramer settings should be made in user mode or user program mode. flash memory area divisions are sh own in table 14.4. to ensure correct operation of the emulation function, the rom for which ram emulation is performed should not be accessed immediately after this register has been mo dified. normal execution of an access immediately after register modification is not guaranteed. bit bit name initial value r/w description 7 to 4 ? all 0 ? reserved these bits are always read as 0. the write value should always be 0. 3 rams 0 r/w ram select specifies selection or non-selection of flash memory emulation in ram. when rams is 1, all flash memory blocks are program/erase-protected. 0: emulation not selected program/erase-protection of all flash memory blocks is disabled. 1: emulation selected program/erase-protection of all flash memory blocks is enabled. 2 1 0 ram2 ram1 ram0 0 0 0 r/w r/w r/w flash memory area selection these bits are used together wit h bit 3 to select the flash memory area to be overlapped with ram (see table 14.4).
rev. 2.00, 03/04, page 391 of 534 table 14.4 flash memory area divisions ram area block name ram2 ram1 ram0 h'000000 to h'000fff eb0 (4 kbytes) 0 0 0 h'001000 to h'001fff eb1 (4 kbytes) 0 0 1 h'002000 to h'002fff eb2 (4 kbytes) 0 1 0 h'003000 to h'003fff eb3 (4 kbytes) 0 1 1 h'004000 to h'004fff eb4 (4 kbytes) 1 0 0 h'005000 to h'005fff eb5 (4 kbytes) 1 0 1 h'006000 to h'006fff eb6 (4 kbytes) 1 1 0 h'007000 to h'007fff eb7 (4 kbytes) 1 1 1 14.3.2 programming/erasing interface parameter the programming/erasing interface parameter speci fies the operating frequ ency, storage place for program data, programming destination address, and erase block and exchanges the processing result for the downloaded on-chip program. this parameter uses the general registers of the cpu (er0 and er1) or the on-chip ram area. the initial value is undefined at a reset or in hardware standby mode. when download, initialization, or on-chip program is executed, registers of the cpu except for r0l are stored. the return value of the processing result is written in r0l. since the stack area is used for storing the registers except for r0l, the st ack area must be saved at the processing start. (a maximum size of a stack area to be used is 132 bytes.) the programming/erasing interface parameter is used in the following four items. 1. download control 2. initialization before programming or erasing 3. programming 4. erasing these items use different parameters. the corre spondence table is shown in table 14.5. the meaning of the bits in fpfr varies in each pro cessing program: initialization, programming, or erasure. for details, see descriptions of fpfr for each process.
rev. 2.00, 03/04, page 392 of 534 table 14.5 parameters and target modes name of parameter abbrevia- tion down load initializa- tion program- ming erasure r/w initial value alloca- tion download pass and fail result dpfr ? ? ? r/w undefined on-chip ram * flash pass and fail result fpfr ? r/w undefined r0l of cpu flash programming/ erasing frequency control fpefeq ? ? ? r/w undefined r0 of cpu flash multipurpose address area fmpar ? ? ? r/w undefined on-chip ram flash multipurpose data destination area fmpdr ? ? ? r/w undefined on-chip ram flash erase block select febs ? ? ? r/w undefined r0l of cpu note: * a single byte of the start address to downloa d an on-chip program, which is specified by ftdar
rev. 2.00, 03/04, page 393 of 534 download control: the on-chip program is automatically downloaded by setting the sco bit to 1. the on-chip ram area to be downloaded is th e 2-kbyte area starting from the address specified by ftdar. download control is set by the program/erase interface registers, and the dpfr parameter indicates the return value. a download pass/fail result parameter (dpfr: si ngle byte of start addres s specified by ftdar) this parameter indicates the return value of the download result. the value of this parameter can be used to determine if downloading is executed or not. since the confirmation whether the sco bit is set to 1 is difficult, the certain determinati on must be performed by writing the single byte of the start address specified by ftdar to the value other than the return value of download (for example, h'ff) before the download st art (before setting the sco bit to 1). bit bit name initial value r/w description 7 to 3 ? ? ? unused return 0 2 ss ? r/w source select error detect only one type for the on-chip program which can be downloaded can be specified. when more than two types of the program are se lected, the program is not selected, or the program is selected without mapping, error is occurred. 0: download program can be selected normally 1: download error is occurred (multi-selection or program which is not mapped is selected) 1 fk ? r/w flash key register error detect returns the check result wh ether the value of fkey is set to h'a5. 0: key setting is normal (fkey = h'a5) 1: setting value of fkey becomes error (fkey = value other than h'a5) 0 sf ? r/w success/fail returns the result whether download is ended normally or not. the determination result whether program that is downloaded to the on-chip ram is read back and then transferred to the on-chip ram is returned. 0: downloading on-chip program is ended normally (no error) 1: downloading on-chip program is ended abnormally (error occurs)
rev. 2.00, 03/04, page 394 of 534 programming/erasing initialization: the on-chip programming/erasing program to be downloaded includes the initialization program. the specified period pulse must be applied when programming or erasing. the specified pulse width is made by the method in which wait loop is configured by the cpu instruction. the operating frequency of the cpu must be set. the initial program is set as a parameter of the programming/erasing program which has downloaded these settings. a flash programming/erasing frequency parameter (fpefeq: general register er0 of cpu) this parameter sets the operating frequency of the cpu. the settable range of the operating frequency in this lsi is 10 to 33 mhz. bit bit name initial value r/w description 31 to 16 ? ? ? unused this bit should be cleared to 0. 15 to 0 f15 to f0 ? r/w frequency set set the operating frequency of the cpu. with the pll multiplication function, set the frequency multiplied. the setting value must be calculated as the following methods. 1. the operating frequency which is shown in mhz units must be rounded in a number to three decimal places and be shown in a number of two decimal places. 2. the value multiplied by 100 is converted to the binary digit and is written to the fpefeq parameter (general register er0). for example, when the oper ating frequency of the cpu is 33.000 mhz, the value is as follows. 1. the number to three decim al places of 33.000 is rounded and the value is thus 33.00. 2. the formula that 33.00 100 = 3300 is converted to the binary digit and b'0000,1100,1110,0100 (h'0ce4) is set to er0.
rev. 2.00, 03/04, page 395 of 534 b flash pass/fail parameter (fpfr: general register r0l of cpu) this parameter indicates the return value of the initialization result. bit bit name initial value r/w description 7 to 2 ? ? ? unused return 0 1 fq ? r/w frequency error detect returns the check result wh ether the specified operating frequency of the cpu is in the range of the supported operating frequency. 0: setting of operating frequency is normal 1: setting of operating frequency is abnormal 0 sf ? r/w success/fail indicates whether initialization is completed normally. 0: initialization is ended normally (no error) 1: initialization is ended abnormally (error occurs) programming execution: when flash memory is programmed, the programming destination address on the user mat must be passed to the programming program in which the program data is downloaded. 1. the start address of the programming destination on the user mat must be stored in a general register er1. this parameter is called as fl ash multipurpose address ar ea parameter (fmpar). since the program data is always in units of 128 bytes, the lower eight bits (a7 to a0) must be h'00 or h'80 as the boundary of the programming start address on the user mat. 2. the program data for the user mat must be prepared in the consecutive area. the program data must be in the consecutive space which can be accessed by using the mov.b instruction of the cpu and in other th an the flash memory space. when data to be programmed does not satisfy 128 bytes, the 128-byte program data must be prepared by filling with the dummy code h'ff. the start address of the area in which the prepared program data is stored must be stored in a general register er0. this parameter is called as flash multipurpose data destination area parameter (fmpdr). for details on the program processing procedure, see section 14.4.2, user program mode.
rev. 2.00, 03/04, page 396 of 534 a flash multipurpose address area parameter (fmpar: general register er1 of cpu) this parameter stores the start address of the programming destination on the user mat. when the address in the area other than flas h memory space is set, an error occurs. the start address of the programming destination must be at the 128-byte boundary. if this boundary condition is not satisfied, an error occu rs. the error occurrence is indicated by the wa bit (bit 1) in fpfr. bit bit name initial value r/w description 31 to 0 moa31 to moa0 ? r/w store the start address of the programming destination on the user mat. the consecutive 128-byte programming is executed star ting from the specified start address of the user mat. therefore, the specified programming start address becomes a 128-byte boundary and moa6 to moa0 are always 0. b flash multipurpose data destination parame ter (fmpdr: general register er0 of cpu): this parameter stores the start address in the ar ea which stores the data to be programmed in the user mat. when the storage destination of the pr ogram data is in flash memory, an error occurs. the error occurrence is indicated by the wd bit in fpfr. bit bit name initial value r/w description 31 to 0 mod31 to mod0 ? r/w store the start address of the area which stores the program data for the user mat. the consecutive 128- byte data is programmed to the user mat starting from the specified start address. c flash pass/fail parameter (fpfr: general register r0l of cpu) this parameter indicates the return value of the program processing result. bit bit name initial value r/w description 7 ? ? ? unused return 0.
rev. 2.00, 03/04, page 397 of 534 bit bit name initial value r/w description 6 md ? r/w programming mode related setting error detect returns the check result that a high level signal is input to the fwe pin and the error protection state is not entered. when the low level signal is input to the fwe pin or the error protection stat e is entered, 1 is written to this bit. the state can be confirmed with the fwe and fler bits in fccs. for conditions to enter the error protection state, see secti on 14.5.3, error protection. 0: fwe and fler settings are normal (fwe = 1, fler = 0) 1: programming cannot be performed (fwe = 0 or fler = 1) 5 ee ? r/w programming execution error detect 1 is returned to this bit when the specified data could not be written because the user mat was not erased. if this bit is set to 1, there is a high possibility that the user mat is partially rewritten. in this case, a fter removing the error factor, erase the user mat. if fmats is set to h'aa and the user boot mat is selected, an error occurs when programming is performed. in this case, both the user mat and user boot mat are not rewritten. programming of the user boot mat should be performed in boot mode or programmer mode. 0: programming has ended normally 1: programming has ended abnormally (programming result is not guaranteed) 4 fk ? r/w flash key register error detect returns the check result of the value of fkey before the start of the programming processing. 0: fkey setting is normal (fkey = h'5a) 1: fkey setting is error (fkey = value other than h'5a) 3 ? ? ? unused returns 0. 2 wd ? r/w write data address detect when the address in the flash memory area is specified as the start address of the storage destination of the program data, an error occurs. 0: setting of write data address is normal 1: setting of write data address is abnormal
rev. 2.00, 03/04, page 398 of 534 bit bit name initial value r/w description 1 wa ? r/w write address error detect when the following items are specified as the start address of the programming destination, an error occurs. ? when the programming destination address in the area other than flash memory is specified ? when the specified address is not in a 128-byte boundary. (the lower eight bits of the address are other than h'00 and h'80.) 0: setting of programming destination address is normal 1: setting of programming destination address is abnormal 0 sf ? r/w success/fail indicates whether the program processing is ended normally or not. 0: programming is ended normally (no error) 1: programming is ended abnormally (error occurs) erasure execution: when flash memory is erased, the erase-block number on the user mat must be passed to the erasing program which is downloaded. this is set to the febs parameter (general register er0). one block is specified from the block number 0 to 11. for details on the erasing processing procedure, see section 14.4.2, user program mode. a flash erase block select parameter (febs: general register er0 of cpu) this parameter specifies the erase-block number. the several block numbers cannot be specified.
rev. 2.00, 03/04, page 399 of 534 bit bit name initial value r/w description 31 to 8 ? ? ? unused these bits should be cleared to h'0. 7 6 5 4 3 2 1 0 eb7 eb6 eb5 eb4 eb3 eb2 eb1 eb0 ? ? ? ? ? ? ? ? r/w r/w r/w r/w r/w r/w r/w r/w erase block set the erase-block number in the range from 0 to 11. 0 corresponds to the eb0 block and 11 corresponds to the eb11 block. an error occurs when the number other than 0 to 11 is set. b flash pass/fail parameter (fpfr: general register r0l of cpu) this parameter returns value of the erasing processing result. bit bit name initial value r/w description 7 ? ? ? unused return 0. 6 md ? r/w programming mode related setting error detect returns the check result that a high level signal is input to the fwe pin and the error protection state is not entered. when the low level signal is input to the fwe pin or the error protection stat e is entered, 1 is written to this bit. the state can be confirmed with the fwe and fler bits in fccs. for conditions to enter the error protection state, see secti on 14.5.3, error protection. 0: fwe and fler settings are normal (fwe = 1, fler = 0) 1: programming cannot be performed (fwe = 0 or fler = 1)
rev. 2.00, 03/04, page 400 of 534 bit bit name initial value r/w description 5 ee ? r/w erasure execution error detect 1 is returned to this bit when the user mat could not be erased or when flash-memory related register settings are partially changed. if this bit is set to 1, there is a high possibility that the user mat is partially erased. in this case, after removing the error factor, erase the user mat. if fmats is set to h'aa and the user boot mat is selected, an error occurs when erasure is performed. in this case, both the user mat and user boot mat are not erased. erasing of the user boot mat should be performed in boot mode or programmer mode. 0: erasure has ended normally 1: erasure has ended abnormally (erasure result is not guaranteed) 4 fk ? r/w flash key register error detect returns the check result of fkey value before start of the erasing processing. 0: fkey setting is normal (fkey = h'5a) 1: fkey setting is error (fkey = value other than h'5a) 3 eb ? r/w erase block select error detect returns the check result wh ether the specified erase- block number is in the block range of the user mat. 0: setting of erase-block number is normal 1: setting of erase-block number is abnormal 2, 1 ? ? ? unused return 0. 0 sf ? r/w success/fail indicates whether the erasing processing is ended normally or not. 0: erasure is ended normally (no error) 1: erasure is ended abnormally (error occurs)
rev. 2.00, 03/04, page 401 of 534 14.4 on-board programming mode when the pin is set in on-board programming mode and the reset start is executed, the on-board programming state that can prog ram/erase the on-chip flash memory is entered. on-board programming mode has three operating modes: b oot mode, user program mode, and user boot mode. for details of the pin setting for entering each mode, see table 14.6. for details of the state transition of each mode for fl ash memory, see figure 14.2. table 14.6 setting on-board programming mode mode setting fwe md2 md1 nmi boot mode 1 0 0 1 user program mode 1 1 1 0/1 user boot mode 1 0 0 0 14.4.1 boot mode boot mode executes programming/erasing user mat and user boot mat by means of the control command and program data transmitted from the host using the on-chip sci. the tool for transmitting the control command and program data must be prepared in the host. the sci communication mode is set to asynchronous mode . when reset start is executed after this lsi?s pin is set in boot mode, the boot program in the microcomputer is initiated. after the sci bit rate is automatically adjusted, the communication with the host is executed by means of the control command method. the system configuration diagram in boot mode is shown in figure 14.6. for details on the pin setting in boot mode, see table 14.6. the nmi and other interrupts are ignored in boot mode. however, the nmi and other interrupts should be disabled in the user system.
rev. 2.00, 03/04, page 402 of 534 host rxd0 txd0 control command, analysis execution software (on-chip) flash memory on-chip ram on-chip sci this lsi boot programming tool and program data control command, program data reply response figure 14.6 system configuration in boot mode sci interface setting by host: when boot mode is initiated, this lsi measures the low period of asynchronous sci-communication data (h'00), which is transmitted consecutively by the host. the sci transmit/receive format is se t to 8-bit data, 1 stop bit, and no parity. this lsi calculates the bit rate of transmission by the host by means of the measured low period and transmits the bit adjustment end sign (1 byte of h'00) to the host. the host must confirm that this bit adjustment end sign (h'00) has been received normally and transmits 1 byte of h'55 to this lsi. when reception is not executed normally, boot mode is initiated again (reset) and the operation described above must be executed. the bit rate between the host and this lsi is not matched by the bit rate of transmission by the host and system clock frequency of this lsi. to operate the sci normally, the transfer bit rate of the host must be set to 4,800 bps, 9,600 bps, or 19,200 bps. the system clock frequency, which can automatically adjust the transfer bit rate of the host and the bit rate of this lsi, is shown in table 14.7. boot mode must be initiated in the range of this system clock. d0 d1 d2 d3 d4 d5 d6 d7 start bit stop bit measure low period (9 bits) (data is h'00) high period of at least 1 bit figure 14.7 automatic-bit-rate adjustment operation of sci
rev. 2.00, 03/04, page 403 of 534 table 14.7 system clock frequency for auto matic-bit-rate adjustment by this lsi bit rate of host system clock frequency 4,800 bps 10 to 33 mhz 9,600 bps 10 to 33 mhz 19,200 bps 10 to 33 mhz state transition diagram: the overview of the state transi tion diagram after boot mode is initiated is shown in figure 14.8. 1. bit rate adjustment after boot mode is initiated, the bit rate of the sci interface is adjusted with that of the host. 2. waiting for inquiry set command for inquiries about user-mat size and configuratio n, mat start address, and support state, the required information is transmitted to the host. 3. automatic erasure of all user mat and user boot mat after inquiries have finished, all user mat and user boot mat are automatically erased. 4. waiting for programming/erasing command ? when the program preparation notice is receiv ed, the state for waiting program data is entered. the programming start address and program data must be transmitted following the programming command. when programming is finished, the programming start address must be set to h'ffffffff and transmitted. then the state for waiting program data is returned to the state of pr ogramming/erasing command wait. ? when the erasure preparation notice is receive d, the state for waiting erase-block data is entered. the erase-block number must be transmitted following the erasing command. when the erasure is finished, the erase-block number must be set to h'ff and transmitted. then the state for waiting erase-block data is returned to th e state for waiting programming/erasing command. the erasure must be used when the specified block is programmed without a reset start after programming is executed in boot mode. when programming can be executed by only one operation, all blocks are erased before the state for waiting programming/erasing/other command is entered. the erasing operation is not required. ? there are many commands other than prog ramming/erasing. examples are sum check, blank check (erasure check), and memory re ad of the user mat/user boot mat and acquisition of current status information. note that memory read of the user mat/user b oot mat can only read the programmed data after all user mat/user boot mat has automatically been erased.
rev. 2.00, 03/04, page 404 of 534 wait for inquiry setting command wait for programming/erasing command bit rate adjustment processing of read/check command boot mode initiation (reset by boot mode) h'00.......h'00 reception h'00 transmission (adjustment completed) (bit rate adjustment) processing of inquiry setting command all user mat and user boot mat erasure wait for program data wait for erase-block data read/check command reception command response (program command reception) (program data transmission) (erasure selection command reception) (program end notice) (erase-block specification) (erasure end selection command reception) inquiry command reception h'55 reception inquiry command response 1. 2. 3. 4. figure 14.8 overview of boot mode state transition diagram
rev. 2.00, 03/04, page 405 of 534 14.4.2 user program mode the user mat can be programmed/erased in user program mode. (the user boot mat cannot be programmed/erased.) programming/erasing is executed by downlo ading the program in the microcomputer. the overview flow is shown in figure 14.9. high voltage is applied to internal flash memory during the programming/erasing processing. therefore, transition to reset or hardware standby must not be executed. doing so may damage or destroy flash memory. if reset is executed accidentally, reset must be released after the reset input period of 100 s which is longer than normal. when programming, program data is prepared programming/erasing procedure program is transferred to the on-chip ram and executed programming/erasing start programming/erasing end make sure that the program data will not overlap the download destination specified by ftdar.. the fwe bit is set to 1 by inputting a high level signal to the fwe pin. programming/erasing is executed only in the on-chip ram. however, if program data is in a consecutive area and can be accessed by the mov.b instruction of the cpu like ram or rom, the program data can be in an external space. after programming/erasing is finished, input a low level signal to the fwe pin and transfer to the hardware protection state. 1. 2. 3. 4. figure 14.9 programmin g/erasing overview flow
rev. 2.00, 03/04, page 406 of 534 on-chip ram address map when pr ogramming/erasing is executed: parts of the procedure program that are made by the user, like download request, programming/erasing procedure, and determination of the result, must be executed in the on-chip ram. the on-chip program that is to be downloaded is all in the on-chip ram. note that area in the on-chip ram must be controlled so that these parts do not overlap. figure 14.10 shows the program area to be downloaded. system use area (15 bytes) < on-chip ram > address area to be downloaded (size : 2 kbytes) unusable area in programming/erasing processing period area that can be used by user dpfr (return value: 1 byte) programming/erasing program entry initialization program entry initialization + programming program or initialization + erasing program area that can be used by user ramtop ftdar setting ftdar setting + 16 ftdar setting + 32 ftdar setting + 2 kbytes ramend figure 14.10 ram map when pr ogramming/erasing is executed
rev. 2.00, 03/04, page 407 of 534 programming procedure in user program mode: the procedures for do wnload, initialization, and programming are shown in figure 14.11. select on-chip program to be downloaded and specify download destination by ftdar set fkey to h'a5 set sco to 1 and execute download dpfr = 0? yes no download error processing set the fpefeq parameter yes end programming procedure program fpfr = 0? no disable interrupts and bus master operation other than cpu clear fkey to 0 programming jsr ftdar setting + 16 yes fpfr = 1? no clear fkey and programming error processing yes required data programming is completed? no set fkey to h'5a clear fkey to 0 1. 2. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15. 1 1 3. download initialization programming initialization jsr ftdar setting + 32 initialization error processing set parameters to er1 and er0 (fmpar and fmpdr) start programming procedure program figure 14.11 programming procedure the procedure program must be executed in an area other than the flash memory to be programmed. especially the part where the sco bit in fccs is set to 1 for downloading must be executed in the on-chip ram. the area that can be executed in the steps of the user procedure program (on-chip ram, user mat, and external space) is shown in section 14.4.4, procedure program and storable area for programming data. the following description assumes the area to be programmed on the user mat is erased and program data is prepared in the consecutive ar ea. when erasing is no t executed, erasing is executed before writing. 128-byte programming is performed in one program processing. when more than 128-byte programming is performed, programming destina tion address/program data parameter is updated in 128-byte units and programming is repeated.
rev. 2.00, 03/04, page 408 of 534 when less than 128-byte programming is performed, data must total 128 bytes by adding the invalid data. if the dummy data to be added is h'ff, the program processing period can be shortened. 1. select the on-chip program to be downloaded and specify a download destination when the ppvs bit of fpcs is set to 1, the programming program is selected. several programming/erasing programs cannot be selected at one time. if several programs are set, download is not performed and a download error is returned to the ss bit in dpfr. the start address of a download destination is specified by ftdar. 2. program h'a5 in fkey if h'a5 is not written to fkey for protection, 1 cannot be set to the sco bit for download request. 3. 1 is set to the sco bit of fccs and then download is executed. to set 1 to the sco bit, the following conditions must be satisfied. ? h'a5 is written to fkey. ? the sco bit writing is executed in the on-chip ram. when the sco bit is set to 1, download is started automatically. when the sco bit is returned to the user procedure program, the sco is cl eared to 0. therefore, the sco bit cannot be confirmed to be 1 in the user procedure program. the download result can be confirmed only by the return value of dpfr. before the sco bit is set to 1, incorrect determination must be prevented by setting the one byte of the start address (to be used as dpfr) specified by ftdar to a value other than the return value (h'ff). when download is executed, particular interrupt processing, which is accompanied by the bank switch as described below, is performed as an internal microcomputer processing. four nop instructions are executed imme diately after the instructions that set the sco bit to 1. ? the user-mat space is switched to the on-chip program storage area. ? after the selection condition of the download program and the ftdar setting are checked, the transfer processing to the on-chi p ram specified by ftdar is executed. ? the sco bit in fccs is cleared to 0. ? the return value is set to the dpfr parameter. ? after the on-chip program storage area is re turned to the user-mat space, the user procedure program is returned. ? in the download processing, the values of general registers of the cpu are held. ? in the download processing, any interrupts are not accepted. however, interrupt requests are held. therefore, wh en the user procedure program is returned, the inte rrupts occur. ? when the level-detection interrupt requests are to be held, interrupts must be input until the download is ended.
rev. 2.00, 03/04, page 409 of 534 ? when hardware standby mode is entered during download processing, the normal download cannot be guaranteed in the on-chip ram. therefore, download must be executed again. ? since a stack area of 128 bytes at the maximum is used, the ar ea must be allocated before setting the sco bit to 1. ? if a flash memory access by th e dmac signal is requested during downloading, the operation cannot be guaranteed. therefore, an access request by the dmac signal must not be generated. 4. fkey is cleared to h'00 for protection. 5. the value of the dpfr parameter must be checked and the download result must be confirmed. ? check the value of the dpfr parameter (one byte of start address of the download destination specified by ftdar). if the value is h'00, download has been performed normally. if the value is not h'00, the source that caused download to fail can be investigated by the description below. ? if the value of the dpfr parameter is the same as before downloading (e.g. h'ff), the address setting of the download destination in ftdar may be abnormal. in this case, confirm the setting of the tder bit (bit 7) in ftdar. ? if the value of the dpfr parameter is different from before downloading, check the ss bit (bit 2) and the fk bit (bit 1) in the dpfr parameter to ensure that the download program selection and fkey setting were normal, respectively. 6. the operating frequency and user branch destination are set to the fpefeq and fubra parameters for initialization. ? the current frequency of the cpu clock is set to the fpefeq parameter (general register er0). the settable range of the fpefeq parameter is 5 to 33 mhz. when the frequency is set to out of this range, an error is returned to the fpfr parameter of the initialization program and initialization is not performed. for details on the frequency setting, see the description in 14.3.2 (2) (a), flash programming/erasing frequency parameter (fpefeq). 7. initialization when a programming program is downloaded, the initialization program is also downloaded to the on-chip ram. there is an entry point of the initialization program in the area from the start address specified by ftdar + 32 bytes of the on-chip ram. the subroutine is called and initialization is executed by using the following steps. mov.l #dltop+32,er2 ; set entry address to er2 jsr @er2 ; call initialization routine nop
rev. 2.00, 03/04, page 410 of 534 ? the general registers other than r0l are held in the initialization program. ? r0l is a return value of the fpfr parameter. ? since the stack area is used in the initialization program, 128-byte stack area at the maximum must be allocated in ram. ? interrupts can be accepted during the execution of the initialization program. the program storage area and stack area in the on-chip ram and register values must not be destroyed. 8. the return value in the initialization program, fpfr (general register r0l) is determined. 9. all interrupts and the use of a bus master (dmac) other than the cpu are prohibited. the specified voltage is applied for the specifi ed time when programmi ng or erasing. if interrupts occur or the bus mastership is moved to other than the cpu during this time, the voltage for more than the specified time will be applied and flash memory may be damaged. therefore, interrupts and bus master ship to the dmac are prohibited. to prohibit the interrupt, bit 7 (i) in the condition code register (ccr) of the cpu should be set to b'1 in interrupt control mode 0 or bits 2 to 0 (i2 to i0) in the extend control register of the cpu should be set to b 111 in interrupt control mode 2. then interrupts other than nmi are held and are not executed. the nmi interrupts must be masked within the user system. the interrupts that are held must be executed after all program processing. when the bus mastership is moved to the dm ac, the error protection state is entered. therefore, taking bus mastership by the dmac is prohibited. 10. fkey must be set to h'5a and the user mat must be prepared for programming. 11. the parameter which is required for programming is set. the start address of the programming destination of the user mat (fmpar) is set to general register er1. the start address of the program data area (fmpdr) is set to general register er0. ? example of the fmpar setting fmpar specifies the programming destination address. when an address other than one in the user mat area is specified, even if the programming program is executed, programming is not executed and an error is returned to the return value parameter fpfr. since the unit is 128 bytes, the lower eight bits of the address must be h'00 or h'80 as the boundary of 128 bytes.
rev. 2.00, 03/04, page 411 of 534 ? example of the fmpdr setting when the storage destination of the program data is flash memory, even if the program execution routine is executed, pr ogramming is not executed and an error is returned to the fpfr parameter. in this case, the program da ta must be transferred to the on-chip ram and then programming must be executed. 12. programming there is an entry point of the programming prog ram in the area from the start address specified by ftdar + 16 bytes of the on-chip ram. the subroutine is called and programming is executed by using the following steps. mov.l #dltop+16,er2 ; set entry address to er2 jsr @er2 ; call programming routine nop ? the general registers other than r0l are held in the programming program. ? r0l is a return value of the fpfr parameter. ? since the stack area is used in the programming program, a stack area of 128 bytes at the maximum must be allocated in ram. 13. the return value in the programming program, fpfr (general register r0l) is determined. 14. determine whether programming of the necessary data has finished. if more than 128 bytes of data are to be programmed, specify fmpar and fmpdr in 128- byte units, and repeat steps 12 to 14. increment the programming destination address by 128 bytes and update the programming data pointer correctly. if an address which has already been programmed is written to again, not only w ill a programming error occur, but also flash memory will be damaged. 15. after programming finishes, clear fkey and specify software protection. if this lsi is restarted by a reset immediat ely after user mat programming has finished, secure the reset period (period of res = 0) of 100 s which is longer than normal.
rev. 2.00, 03/04, page 412 of 534 erasing procedure in user program mode: the procedures for download, initialization, and erasing are shown in figure 14.12. set fkey to h'a5 set sco to 1 and execute download dpfr = 0? yes no download error processing set the fpefeq parameter yes end erasing procedure program fpfr = 0 ? no initialization error processing disable interrupts and bus master operation other than cpu clear fkey to 0 set febs parameter yes fpfr = 1 ? no clear fkey and erasing error processing yes required block erasing is completed? no set fkey to h'5a clear fkey to 0 1. 2. 3. 4. 5. 6. 1 1 download initialization erasing initialization jsr ftdar setting + 32 erasing jsr ftdar setting + 16 select on-chip program to be downloaded and specify download destination by ftdar start erasing procedure program figure 14.12 erasing procedure the procedure program must be executed in an area other than the user mat to be erased. especially the part where the sco bit in fccs is set to 1 for downloading must be executed in the on-chip ram. the area that can be executed in the steps of the user procedure program (on-chip ram, user mat, and external space) is shown in section 14.4.4, procedure program and storable area for programming data. for the downloaded on-chip program area, refer to the ram map for programming/erasing in figure 14.10. a single divided block is erased by one erasing processing. for block divisions, refer to figure 14.4. to erase two or more blocks, update the erase block number and perform the erasing processing for each block.
rev. 2.00, 03/04, page 413 of 534 1. select the on-chip program to be downloaded set the epvb bit in fecs to 1. several programming/erasing programs cannot be selected at one time. if several programs are set, download is not performed and a download error is reported to the ss bit in the dpfr parameter. specify the start address of a do wnload destination by ftdar. the procedures to be carried out after setting fkey, e.g. download and initialization, are the same as those in the programming procedure. fo r details, refer to programming procedure in user program mode in section 14.4.2, sub-section (2). the procedures after setting parameters for erasing programs are as follows: 2. set the febs parameter necessary for erasure set the erase block number of the user mat in the flash eras e block select parameter febs (general register er0). if a valu e other than an erase block number of the user mat is set, no block is erased even though the erasing program is executed, and an error is returned to the return value parameter fpfr. 3. erasure similar to as in programming, there is an entr y point of the erasing program in the area from the start address of a download destinatio n specified by ftdar + 16 bytes of on-chip ram. the subroutine is called and erasing is executed by using the following steps. mov.l #dltop+16,er2 ; set entry address to er2 jsr @er2 ; call erasing routine nop the general registers other than r0l are held in the erasing program. r0l is a return value of the fpfr parameter. since the stack area is used in the erasin g program, a stack area of 128 bytes at the maximum must be allocated in ram. 4. the return value in the er asing program, fpfr (general register r0l) is determined. 5. determine whether erasure of the necessary blocks has completed. if more than one block is to be erased, update the febs parameter and repeat steps 2 to 5. blocks that have already been erased can be erased again. 6. after erasure completes, clear fk ey and specify software protection. if this lsi is restarted by a reset immediately after user mat erasure has completed, secure the reset period (period of res = 0) of 100 s which is longer than normal.
rev. 2.00, 03/04, page 414 of 534 erasing and programming pro cedure in user program mode: by changing the on-chip ram address of the download destination in ftdar, the erasing program and programming program can be downloaded to se parate on-chip ram areas. figure 14.13 shows a repeating procedure of erasing and programming. yes no 1 1 erasing program download programming program download erasing/ programming start procedure program specify a download destination of erasing program by ftdar download erasing program initialize erasing program specify a download destination of programming program by ftdar download programming program initialize programming program end procedure program erase relevant block (execute erasing program) set fmpdr to program relevant block (execute programming program) confirm operation end ? figure 14.13 repeating procedure of erasing and programming in the above procedure, download and initialization are performed only once at the beginning. in this kind of operation, note the following: ? be careful not to damage on-chip ram with overlapped settings. in addition to the erasing program area and programming program area, areas for the user procedure programs, work area, and stack area are reserved in on-chip ram. do not make settings that will overwrite data in these areas. ? be sure to initialize both the erasing program and programming program. initialization by setting the fpefeq parameter must be performed for both the erasing program and the programming program. initialization must be executed for both entry addresses: (download start address for erasing program) + 32 bytes and (download start address for programming program) + 32 bytes.
rev. 2.00, 03/04, page 415 of 534 14.4.3 user boot mode this lsi has user boot mode which is initiated with different mode pin settings than those in boot mode or user program mode. user boot mode is a user-arbitrary boot mode, unlike boot mode that uses the on-chip sci. only the user mat can be programmed/erased in user boot mode. programming/erasing of the user boot mat is only enabled in boot mode or programmer mode. user boot mode initiation: for the mode pin settings to start up user boot mode, see table 14.6. when the reset start is executed in user boot mo de, the built-in check routine runs. the user mat and user boot mat states are ch ecked by this check routine. while the check routine is running, nmi and all other interrupts cannot be accepted. next, processing starts from the execution start address of the reset vector in the user boot mat. at this point, h'aa is set to fmats because the execution mat is the user boot mat. user mat programming in user boot mode: for programming the user mat in user boot mode, additional processing made by setting fmats is required: switching from user-boot-mat selection state to user-mat sel ection state, and switching back to user-boot-mat selection state after programming completes. figure 14.14 shows the procedure for programming the user mat in user boot mode.
rev. 2.00, 03/04, page 416 of 534 set fkey to h'a5 dpfr = 0 ? yes no download error processing set the fpefeq and fubra parameters initialization jsr ftdar setting + 32 yes end programming procedure program fpfr = 0 ? no initialization error processing disable interrupts and bus master operation other than cpu clear fkey to 0 set parameter to er0 and er1 (fmpar and fmpdr) programming jsr ftdar setting + 16 yes fpfr = 0 ? no yes required data programming is completed? no set fkey to h'a5 clear fkey to 0 1 1 download initialization programming mat switchover mat switchover set fmats to value other than h'aa to select user mat set sco to 1 and execute download clear fkey and programming error processing * set fmats to h'aa to select user boot mat user-boot-mat selection state user-mat selection state user-boot-mat selection state note: * the mat must be switched by fmats to perform the programming error processing in the user boot mat. start programming procedure program select on-chip program to be downloaded and specify download destination by ftdar figure 14.14 procedu re for programming user ma t in user boot mode the difference between the programming procedures in user program mode and user boot mode is whether the mat is switched or not as shown in figure 14.14. in user boot mode, the user b oot mat can be seen in the flas h memory space with the user mat hidden in the background. the user mat and us er boot mat are switched only while the user mat is being programmed. because the user boot mat is hidden while the user mat is being programmed, the procedure program must be locat ed in an area other than flash memory. after programming completes, switch the mats again to return to the first state. mat switching is enabled by writing a specific value to fmats. however note that while the mats are being switched, the lsi is in an unstabl e state, e.g. access to a mat is not allowed until mat switching is completed, and if an interrupt occurs, from which mat th e interrupt vector is read is undetermined. perform mat switching in accordance with the description in section 14.6, switching between user mat and user boot mat.
rev. 2.00, 03/04, page 417 of 534 except for mat switching, the programming procedure is the same as that in user program mode. the area that can be executed in the steps of the user procedure program (on-chip ram, user mat, and external space) is shown in section 14.4.4, procedure program and storable area for programming data. user mat erasing in user boot mode: for erasing the user mat in user boot mode, additional processing made by setting fmats is required: switching from user-boot-mat selection state to user-mat selection state, and switching back to user-boot-mat select ion state after erasing completes. figure 14.15 shows the procedure for erasing the user mat in user boot mode. yes no start erasing procedure program set fkey to h'a5 yes no download error processing set the fpefeq and fubra parameters end erasing procedure program fpfr = 0 ? initialization error processing disable interrupts and bus master operation other than cpu clear fkey to 0 set febs parameter yes no clear fkey and erasing error processing * yes required block erasing is completed? no set fkey to h'a5 clear fkey to 0 1 1 download initialization erasing set fmats to value other than h'aa to select user mat set sco to 1 and execute download set fmats to h'aa to select user boot mat user-boot-mat selection state user-mat selection state user-boot-mat selection state note: * the mat must be switched by fmats to perform the erasing error processing in the user boot mat. mat switchover mat switchover dpfr = 0 ? initialization jsr ftdar setting + 32 programming jsr ftdar setting + 16 fpfr = 0 ? select on-chip program to be downloaded and specify download destination by ftdar figure 14.15 procedure for eras ing user mat in user boot mode the difference between the erasing procedures in user program mode and user boot mode depends on whether the mat is switched or not as shown in figure 14.15.
rev. 2.00, 03/04, page 418 of 534 mat switching is enabled by writing a specific value to fmats. however note that while the mats are being switched, the lsi is in an unstabl e state, e.g. access to a mat is not allowed until mat switching is completed, and if an interrupt occurs, from which mat the interrupt vector is read is undetermined. perform mat switching in accordance with the description in section 14.6, switching between user mat and user boot mat. except for mat switching, the erasing procedure is the same as that in user program mode. the area that can be executed in the steps of the user procedure program (on-chip ram, user mat, and external space) is shown in section 14.4.4, procedure program and storable area for programming data. 14.4.4 procedure program and storable area for programming data in the descriptions in the previous section, the programming/erasing procedure programs and storable areas for program data are assumed to be in the on-chi p ram. however, the program and the data can be stored in and executed from other areas, such as part of flash memory which is not to be programmed or erased, or some where in the extern al address space. conditions that apply to programming/erasing: 1. the on-chip programming/erasing program is downloaded from the address in the on-chip ram specified by ftdar, therefore, this area is not available for use. 2. the on-chip programming/erasing program will use 128 bytes at the maximum as a stack. so, make sure that this area is secured. 3. download by setting the sco bit to 1 will lead to switching of the ma t. if, therefore, this operation is used, it should be executed from the on-chip ram. 4. the flash memory is accessible until the start of pr ogramming or erasing, that is, until the result of downloading has been determined. when in a mode in which the external address space is not accessible, such as single-chi p mode, the required pr ocedure programs, nmi handling vector and nmi handler should be transferred to the on-chip ram before programming/erasing of the flash memory starts. 5. the flash memory is not acce ssible during programming/erasing operations, therefore, the operation program is downloaded to the on-chip ram to be executed. the nmi-handling vector and programs such as that which ac tivate the operation prog ram, and nmi handler should thus be stored in on-chip memory other than flash memory or the external address space.
rev. 2.00, 03/04, page 419 of 534 6. after programming/erasing, the flash memory should be inhibited until fkey is cleared. the reset state ( res = 0) must be in place for more than 100 s when the lsi mode is changed to reset on completion of a programming/erasing operation. transitions to the reset state, and hardware standby mode are inhibited during programming/erasing. when the re set signal is accidentally input to the chip, a longer period in the reset state than usual (100 s) is needed before the reset signal is released. 7. switching of the mats by fmats should be needed when programming/erasing of the user boot mat is operated in user-boot mode. the program which switches the mats should be executed from the on-chip ram. see section 14.6, switching between user mat and user boot mat. please make sure you know which mat is selected when switching between them. 8. when the data storable area indicated by programming parameter fmpdr is within the flash memory area, an error will occur even when the data stored is normal. therefore, the data should be transferred to the on-chip ram to place the address that fmpdr indicates in an area other than the flash memory. in consideration of these conditions, there are thre e factors; operating mode , the bank structure of the user mat, and operations. the areas in which the programming data can be stored for execution are shown in tables. table 14.8 executable mat initiated mode operation user program mode user boot mode * programming table 14.9 (1) table 14.9 (3) erasing table 14.9 (2) table 14.9 (4) note: * programming/erasing is possible to user mats.
rev. 2.00, 03/04, page 420 of 534 table 14.9 (1) useable area for pr ogramming in user program mode storable /executable area selected mat item on-chip ram user mat external space (expanded mode) user mat embedded program storage area storage area for program data * ? ? operation for selection of on-chip program to be downloaded operation for writing h'a5 to fkey execution of writing sc0 = 1 to fccs (download) operation for fkey clear determination of download result operation for download error operation for settings of initial parameter execution of initialization determination of initialization result operation for initialization error nmi handling routine operation for inhibit of interrupt operation for writing h'5a to fkey operation for settings of program parameter
rev. 2.00, 03/04, page 421 of 534 storable /executable area selected mat item on-chip ram target flash memory external space (expanded mode) user mat embedded program storage area execution of programming determination of program result operation for program error operation for fkey clear note: * transferring the data to the on-chip ram enables this area to be used.
rev. 2.00, 03/04, page 422 of 534 table 14.9 (2) useable area for erasure in user program mode storable /executable area selected mat item on-chip ram user mat external space (expanded mode) user mat embedded program storage area operation for selection of on-chip program to be downloaded operation for writing h'a5 to fkey execution of writing sc0 = 1 to fccs (download) operation for fkey clear determination of download result operation for download error operation for settings of initial parameter execution of initialization determination of initialization result operation for initialization error nmi handling routine operation for inhibit of interrupt operation for writing h'5a to fkey operation for settings of erasure parameter execution of erasure determination of erasure result
rev. 2.00, 03/04, page 423 of 534 storable /executable area selected mat item on-chip ram user mat external space (expanded mode) user mat embedded program storage area operation for erasure error operation for fkey clear
rev. 2.00, 03/04, page 424 of 534 table 14.9 (3) useable area for programming in user boot mode storable/executable area selected mat item on-chip ram user boot mat external space (expanded mode) user mat user boot mat embedded program storage area storage area for program data * 1 ? ? ? operation for selection of on-chip program to be downloaded operation for writing h'a5 to fkey execution of writing sc0 = 1 to fccs (download) operation for fkey clear determination of download result operation for download error operation for settings of initial parameter execution of initialization determination of initialization result operation for initialization error nmi handling routine operation for interrupt inhibit switching mats by fmats operation for writing h'5a to fkey
rev. 2.00, 03/04, page 425 of 534 storable/executable area selected mat item on-chip ram user boot mat external space (expanded mode) user mat user boot mat embedded program storage area operation for settings of program parameter execution of programming determination of program result operation for program error * 2 operation for fkey clear switching mats by fmats notes: 1. transferring the data to the on -chip ram enables this area to be used. 2. switching fmats by a program in the on-chip ram enables this area to be used.
rev. 2.00, 03/04, page 426 of 534 table 14.9 (4) useable area fo r erasure in user boot mode storable/executable area selected mat item on-chip ram user boot mat external space (expanded mode) user mat user boot mat embedded program storage area operation for selection of on-chip program to be downloaded operation for writing h'a5 to fkey execution of writing sc0 = 1 to fccs (download) operation for fkey clear determination of download result operation for download error operation for settings of initial parameter execution of initialization determination of initialization result operation for initialization error nmi handling routine operation for interrupt inhibit switching mats by fmats operation for writing h'5a to fkey operation for settings of erasure parameter
rev. 2.00, 03/04, page 427 of 534 storable/executable area selected mat item on-chip ram user boot mat external space (expanded mode) user mat user boot mat embedded program storage area execution of erasure determination of erasure result operation for erasure error * operation for fkey clear switching mats by fmats note: * switching fmats by a program in the on- chip ram enables this area to be used.
rev. 2.00, 03/04, page 428 of 534 14.5 protection there are two kinds of flash memory program/erase protection: hardware and software protection. 14.5.1 hardware protection programming and erasing of flash memory is forcibly disabled or suspended by hardware protection. in this state, the downloading of an on-chip program and initialization are possible. however, an activated program for programming or erasure cannot program or erase locations in a user mat, and the error in programming/er asing is reported in the parameter fpfr. table 14.10 hardware protection function to be protected item description download program/erase fwe pin protection ? when a low level signal is input to the fwe pin, the fwe bit in fccs is cleared and the program/erase- protected stat e is entered. ? reset/standby protection ? the program/erase interface registers are initialized in the reset state (including a reset by the wdt) and standby mode and the program/erase- protected stat e is entered. ? the reset state will not be entered by a reset using the res pin unless the res pin is held low until oscillation has stabilized after power is initially supplied. in the case of a reset during operation, hold the res pin low for the res pulse width that is specified in the section on ac characteristics. if a reset is input during programming or erasure, data values in the flash memory are not guaranteed. in this case, execute erasure and then execute program again.
rev. 2.00, 03/04, page 429 of 534 14.5.2 software protection software protection is set up in any of two ways: by disabling the downloading of on-chip programs for programming and erasing and by means of a key code. table 14.11 software protection function to be protected item description download program/erase protection by the sco bit ? the program/erase-protected state is entered by clearing the sco bit in fccs which disables the downloading of the programming/erasing programs. protection by the fkey register ? downloading and programming/erasing are disabled unless the required key code is written in fkey. different key codes are used for downloading and for programming/erasing. 14.5.3 error protection error protection is a mechanism for aborting programming or erasure when an error occurs, in the form of the microcomputer entering runaway duri ng programming/erasing of the flash memory or operations that are not according to the establishe d procedures for progra mming/erasing. aborting programming or erasure in such cases prevents damage to the flash memory due to excessive programming or erasing. if the microcomputer malfunctions during programming/erasing of the flash memory, the fler bit in the fccs register is set to 1 and the erro r-protection state is entered, and this aborts the programming or erasure. the fler bit is set in the following conditions: 1. when an interrupt such as nmi occurs during programming/erasing. 2. when the flash memory is read during programming/erasing (including a vector read or an instruction fetch). 3. when a sleep instruction (including software-standby mode) is executed during programming/erasing. 4. when a bus master other than the cpu, such as the dmac, gets bus mastership during programming/erasing.
rev. 2.00, 03/04, page 430 of 534 error protection is cancelled only by a reset or by hardware-standby mode. note that the reset should be released after the reset period of 100 s which is longer than normal. since high voltages are applied during programming/erasing of the flash memory, some voltage may remain after the error-protection state has been entered. fo r this reason, it is necessary to reduce the risk of damage to the flash memory by extending the reset period so that the charge is released. the state-transition diagram in figure 14.16 shows transitions to and from the error-protection state. reset or hardware standby (hardware protection) program mode erase mode error protection mode error-protection mode (software standby) read disabled programming/erasing enabled fler = 0 read disabled programming/erasing disabled fler = 0 read enabled programming/erasing disabled fler = 1 read disabled programming/erasing disabled fler = 1 = 0 or = 0 error occurrence error occurred (software standby) = 0 or = 0 software-standby mode cancel software-standby mode = 0 or = 0 program/erase interface register is in its initial state. program/erase interface register is in its initial state. figure 14.16 transitions to error-protection state
rev. 2.00, 03/04, page 431 of 534 14.6 switching between user mat and user boot mat it is possible to alternate between the user ma t and user boot mat. however, the following procedure is required because these mats are allocated to address 0. (switching to the user boot mat disables programming and erasing. programming of the user boot mat should take place in bo ot mode or programmer mode.) 1. mat switching by fmats should always be executed from the on-chip ram. 2. to ensure that the mat that has been switched to is accessible, execute four nop instructions in the on-chip ram immediately after writing to fmats of the on-chip ram (this prevents access to the flash memory during mat switching). 3. if an interrupt has occurred during switching, there is no guarantee of which memory mat is being accessed. always mask the maskable inte rrupts before switch ing between mats. in addition, configure the system so that nmi interrupts do not occur during mat switching. 4. after the mats have been switched, take care because the interrupt vector table will also have been switched. if interrupt processing is to be the same before and after mat switching, transfer the interrupt-processing routines to the on-chip ram and set the weinte bit in fccs to place the inte rrupt-vector table in the on-chip ram. 5. memory sizes of the user mat and user boot mat are different. when accessing the user boot mat, do not access addresses above the to p of its 8-kbyte memory space. if access goes beyond the 8-kbyte space, the values read are undefined. < user mat >< on-chip ram >< user boot mat > procedure for switching to the user boot mat procedure for switching to the user mat procedure for switching to the user boot mat (1) mask interrupts (2) write h'aa to fmats. (3) execute four nop instructions before accessing the user boot mat. procedure for switching to the user mat (1) mask interrupts (2) write a value other than h'aa to fmats. (3) execute four nop instructions before accessing the user mat. figure 14.17 switching between the user mat and user boot mat
rev. 2.00, 03/04, page 432 of 534 14.7 flash memory emulation in ram 14.7.1 emulation in ram making a setting in the ram emulation register (ramer) enables part of ram to be overlapped onto the flash memory area so that data to be wr itten to flash memory can be emulated in ram in realtime. after the ramer setting has been made , accesses can be made from the flash memory area or the ram area overlapping flash memory. emulation can be performed in user mode and user program mode. figure 14.18 shows an example of emulation of realtime flash memory. start of emulation program set ramer ye s no end of emulation program clear ramer execute application program tuning ok? write tuning data to overlap ram write to flash memory emulation block figure 14.18 flowchart for flash memory emulation in ram
rev. 2.00, 03/04, page 433 of 534 14.7.2 ram overlap h'00000 h'01000 h'02000 h'03000 h'04000 h'05000 h'06000 h'07000 h'08000 h'3ffff flash memor eb8 to eb11 this area can be accessed from both the ram area and flash memory area eb0 eb1 eb2 eb3 eb4 eb5 eb6 eb7 h'ff7000 h'ff7fff h'ffefff on-chip ram figure 14.19 example of ram overlap operation (256-kbyte flash memory) as the flash memory area to be emulated, bits ram2 to ram0 se lect one area among eight areas, eb0 to eb7, in bank 1 of user mat. figure 14.19 shows an example in which flash memory block area, eb1, is overlapped. 1. set bits rams, ram2, ram1, and ram0 in ramer to 1, 0, 0, 1, to overlap part of ram onto the area (eb1) for which realtime programming is required. 2. realtime programming is performed using the overlapping ram. 3. after the program data has been confirmed, the rams bit is cleared, releasing ram overlap. 4. the data written in the ov erlapping ram is written into the flash memory space (eb1). notes: 1. when the rams bit is set to 1, program/erase-protection is enables for all flash memory blocks regardless of the value of ram2, ram1, and ram0 (emulation protection). when actually programming a flash memory area, the rams bit should be cleared to 0. 2. the ram area cannot be erased by execu tion of software in acc ordance with the erase algorithm while flash memory emulation in ram is being used. 3. block area eb0 includes the vector table. when performing ram emulation, the vector table is needed by the overlap ram.
rev. 2.00, 03/04, page 434 of 534 14.8 programmer mode along with its on-board programming mode, this lsi also has a programmer mode as a further mode for the writing and erasing of programs and data. in the programmer mode, a general- purpose prom programmer can freely be used to write programs to the on-chip rom. program/erase is possible on the user mat an d user boot mat. the prom programmer must support renesas technology?s microcomputers with 258-kbyte flash memory as a device type*. figure 14.20 shows a memory map in programmer mode. a status-polling system is adopted for operati on in automatic program, automatic erase, and status-read modes. in the status-read mode, details of the system's internal signals are output after execution of automatic programming or automatic erasure. in programm er mode, provide a 12- mhz input-clock signal. note: * in this lsi, set the programming voltage of the prom programmer to 3.3 v. mcu mode this lsi on-chip rom area h'000000 programmer mode h'00000 h'03ffff h'3ffff figure 14.20 memory map in programmer mode
rev. 2.00, 03/04, page 435 of 534 14.9 serial communication interface specification for boot mode initiating boot mode enables the boot program to communicate with the host by using the internal sci. the serial communication inte rface specification is shown below. status: the boot program has three states. 1. bit-rate-adjustment state in this state, the boot program adjusts the bit rate to communicate with the host. initiating boot mode enables starting of the boot program and entry to the bit-rate-adjustment state. the program receives the command from the host to ad just the bit rate. after adjusting the bit rate, the program enters the in quiry/selection state. 2. inquiry/selection state in this state, the boot program responds to inquiry commands from the host. the device name, clock mode, and bit rate are selected. after selection of these settings, the program is made to enter the programming/erasing state by the command for a transition to the programming/erasing state. the program transfers the libraries required for erasure to the on- chip ram and erases the user mats and user boot mats before the transition. 3. programming/erasing state programming and erasure by the boot program take place in this state. the boot program is made to transfer the programming/erasing programs to the ram by commands from the host. sum checks and blank checks are executed by sending these comm ands from the host. these boot program states are shown in figure 14.21.
rev. 2.00, 03/04, page 436 of 534 transition to programming/erasing programming/erasing wait checking inquiry response erasing programming reset bit-rate-adjustment state operations for erasing user mats and user boot mats operations for inquiry and selection operations for programming operations for checking operations for erasing operations for response inquiry/response wait figure 14.21 boot program states
rev. 2.00, 03/04, page 437 of 534 bit-rate-adjustment state: the bit rate is calculated by meas uring the period of transfer of a low-level byte (h'00) from the host. the bit rate can be changed by the command for a new bit rate selection. after the bit rate has been adjusted, the boot program enters the inquiry and selection state. the bit-rate-adjustmen t sequence is shown in figure 14.22. host boot program h'00 (30 times maximum) h'e6 (boot response) measuring the 1-bit length h'00 (completion of adjustment) h'55 (h'ff (error)) figure 14.22 bit-rate-adjustment sequence communications protocol: after adjustment of the bit rate, the protocol for communications between the host and the boot program is as shown below. 1. one-byte commands and one-byte responses these commands and responses are comprised of a single byte. these are consists of the inquiries and the ack for successful completion. 2. n-byte commands or n-byte responses these commands and responses are comprised of n bytes of data. these are selections and responses to inquiries. the amount of programming data is not included under this heading because it is determined in another command. 3. error response the error response is a response to inquiries. it consists of an error response and an error code and comes two bytes. 4. programming of 128 bytes the size is not specified in commands. the size of n is in dicated in response to the programming unit inquiry. 5. memory read response this response consists of four bytes of data.
rev. 2.00, 03/04, page 438 of 534 command or response size data checksum error response error code command or response error response n-byte command or n-byte response one-byte command or one-byte response address command data (n bytes) checksum 128-byte programming size response data checksum memory read response figure 14.23 communication protocol format ? command (one byte): commands including inquiries, selection, programming, erasing, and checking ? response (one byte): response to an inquiry ? size (one byte): the amount of data for transmission excluding the command, amount of data, and checksum ? checksum (one byte): th e checksum is calculated so that the total of all values from the command byte to the sum byte becomes h'00. ? data (n bytes): detailed data of a command or response ? error response (one byte): error response to a command ? error code (one byte): type of the error ? address (four bytes): address for programming ? data (n bytes): data to be programmed (the size is indicated in the response to the programming unit inquiry.) ? size (four bytes): four-byte response to a memory read
rev. 2.00, 03/04, page 439 of 534 inquiry and selection states: the boot program returns information from the flash memory in response to the host's inquiry commands and sets the device code, clock mode, and bit rate in response to the host's selection command. inquiry and selection commands are listed below. table 14.12 inquiry and selection commands command command name description h'20 supported device inquiry inquiry regarding device codes h'10 device selection sele ction of device code h'21 clock mode inquiry inquiry regarding numbers of clock modes and values of each mode h'11 clock mode selection indication of the selected clock mode h'22 multiplication ratio inquiry i nquiry regarding the number of frequency- multiplied clock types, the number of multiplication ratios, and the values of each multiple h'23 operating clock frequency inquiry i nquiry regarding the maximum and minimum values of the main clock and peripheral clocks h'24 user boot mat information inquiry i nquiry regarding the number of user boot mats and the start and last addresses of each mat h'25 user mat information inquiry inquiry regarding the a number of user mats and the start and last addresses of each mat h'26 block for erasing information inquiry inquiry regarding the number of blocks and the start and last addresses of each block h'27 programming unit inquiry inquiry regarding the unit of programming data h'3f new bit rate selection selection of new bit rate h'40 transition to programming/erasing state erasing of user mat and user boot mat, and entry to programming/erasing state h'4f boot program status inquiry inquiry into the oper ated status of the boot program the selection commands, which are device selection (h'10), clock mode selection (h'11), and new bit rate selection (h'3f), should be sent from the host in that order. these commands will certainly be needed. when two or more selection commands are sent at once, the last command will be valid.
rev. 2.00, 03/04, page 440 of 534 all of these commands, except for the boot program status inquiry command (h'4f), will be valid until the boot program receives th e programming/erasing transition (h'40). the host can choose the needed commands out of the commands and inquiries listed above. the boot program status inquiry command (h'4f) is valid after the boot program has received the programming/erasing transition command (h'40). (a) supported device inquiry the boot program will return the device codes of supported devices and the product code in response to the supported device inquiry. command h'20 ? command, h'20, (one byte): inquiry regarding supported devices response h'30 size number of devices number of characters device code product name sum ? response, h'30, (one byte): response to the supported device inquiry ? size (one byte): number of bytes to be transmitted, excluding the command, size, and checksum, that is, the amount of data contribu tes by the number of devices, characters, device codes and product names ? number of devices (one byte): the number of device types supported by the boot program ? number of characters (one byt e): the number of characters in the device codes and boot program's name ? device code (four bytes): ascii code of the supporting product ? product name (n bytes): type name of the boot program in ascii-coded characters ? sum (one byte): checksum the checksum is calculated so that the total number of all values from the command byte to the sum byte becomes h'00.
rev. 2.00, 03/04, page 441 of 534 (b) device selection the boot program will set the supported device to the specified device code. the program will return the selected device code in response to the inquiry after this setting has been made. command h'10 size device code sum ? command, h'10, (one byte): device selection ? size (one byte): amount of device-code data this is fixed at 2 ? device code (four bytes): device code (ascii code) returned in response to the supported device inquiry ? sum (one byte): checksum response h'06 ? response, h'06, (one byte): respon se to the device selection command ack will be returned when the device code matches. error response h'90 error ? error response, h'90, (one byte): error response to the device selection command error : (one byte): error code h'11: sum check error h'21: device code error, that is, the device code does not match (c) clock mode inquiry the boot program will return the supported clock modes in response to the clock mode inquiry. command h'21 ? command, h'21, (one byte): inquiry regarding clock mode response h'31 size number of modes mode sum ? response, h'31, (one byte): response to the clock-mode inquiry ? size (one byte): amount of data that represents the number of modes and modes ? number of clock modes (one byte): the number of supported clock modes h'00 indicates no clock mode or the device allows to read the clock mode. ? mode (one byte): values of the supported clock modes (i.e. h'01 means clock mode 1.) ? sum (one byte): checksum
rev. 2.00, 03/04, page 442 of 534 (d) clock mode selection the boot program will set the specified clock mode. the program will return the selected clock- mode information after this setting has been made. the clock-mode selection command should be sent after the device-selection commands. command h'11 size mode sum ? command, h'11, (one byte): selection of clock mode ? size (one byte): amount of data that represents the modes ? mode (one byte): a clock mode returned in reply to the supported clock mode inquiry. ? sum (one byte): checksum response h'06 ? response, h'06, (one byte): response to the clock mode selection command ack will be returned when the clock mode matches. error response h'91 error ? error response, h'91, (one byte) : error response to the clock mode selection command ? error : (one byte): error code h'11: checksum error h'22: clock mode error, that is, the clock mode does not match. even if the clock mode numbers are h'00 and h'01 by a clock mode inquiry, the clock mode must be selected using these respective values. (e) multiplication ratio inquiry the boot program will return the supported multiplication and division ratios. command h'22 ? command, h'22, (one byte): inquiry regarding multiplication ratio response h'32 size number of types number of multiplication ratios multiplica- tion ratio sum
rev. 2.00, 03/04, page 443 of 534 ? response, h'32, (one byte): response to the multiplication ratio inquiry ? size (one byte): the amount of data that re presents the number of clock sources and multiplication ratios and the multiplication ratios ? number of types (one byte): the number of supported multiplied clock types (e.g. when there are two multiplied clock types, which are the main and peripheral clocks, the number of types will be h'02.) ? number of multiplication ratios (one byte): the number of multiplication ratios for each type (e.g. the number of multiplication ratios to which the main clock can be set and the peripheral clock can be set.) ? multiplication ratio (one byte) multiplication ratio: the value of the multiplication ratio (e.g. when the clock-frequency multiplier is four, the value of multiplication ratio will be h'04.) division ratio: the inverse of the division ratio, i.e. a negative number (e.g. when the clock is divided by two, the value of division ratio will be h'fe. h'fe = d'-2) the number of multiplication ratios returned is the same as the number of multiplication ratios and as many groups of data ar e returned as there are types. ? sum (one byte): checksum (f) operating clock frequency inquiry the boot program will return the number of operating clock frequencies, and the maximum and minimum values. command h'23 ? command, h'23, (one byte): inquiry regarding operating clock frequencies response h'33 size number of operating clock frequencies minimum value of operating clock frequency maximum value of operating clock frequency sum ? response, h'33, (one byte): response to operating clock frequency inquiry ? size (one byte): the number of bytes that re presents the minimum values, maximum values, and the number of frequencies. ? number of operating clock frequencies (one byte): the number of supported operating clock frequency types (e.g. when there are two operating clock frequen cy types, which are the main and peripheral clocks, the number of types will be h'02.)
rev. 2.00, 03/04, page 444 of 534 ? minimum value of operating clock frequency (two bytes): the minimum value of the multiplied or divided clock frequency. the minimum and maximum values represent the values in mhz, valid to the hundredths place of mhz, and multiplied by 100. (e.g. when the value is 20.00 mhz, it will be 2000, which is h'07d0.) ? maximum value (two bytes): maximum value among the multiplied or divided clock frequencies. there are as many pairs of minimum and ma ximum values as there are operating clock frequencies. ? sum (one byte): checksum (g) user boot mat information inquiry the boot program will return the number of user boot mats and their addresses. command h'24 ? command, h'24, (one byte): inquiry regarding user boot mat information response h'34 size number of areas area-start address area-last address sum ? response, h'34, (one byte): response to user boot mat information inquiry ? size (one byte): the number of bytes that repr esents the number of areas, area-start addresses, and area-last address ? number of areas (one byte): the number of consecutive user boot mat areas when user boot mat areas are consecutive, the number of areas returned is h'01. ? area-start address (four byte) : start address of the area ? area-last address (four byte) : last address of the area there are as many groups of data representing the start and last addre sses as there are areas. ? sum (one byte): checksum
rev. 2.00, 03/04, page 445 of 534 (h) user mat information inquiry the boot program will return the number of user mats and their addresses. command h'25 ? command, h'25, (one byte): inquiry regarding user mat information response h'35 size number of areas start address area last address area sum ? response, h'35, (one byte): response to the user mat information inquiry ? size (one byte): the number of bytes that re presents the number of areas, area-start address and area-last address ? number of areas (one byte): the nu mber of consecutive user mat areas when the user mat areas are consecutive, the number of areas is h'01. ? area-start address (four bytes ): start address of the area ? area-last address (four bytes): last address of the area there are as many groups of data representing the start and last addre sses as there are areas. ? sum (one byte): checksum (i) erased block information inquiry the boot program will return the number of erased blocks and their addresses. command h'26 ? command, h'26, (two bytes): inquiry regarding erased block information response h'36 size number of blocks block start address block last address sum ? response, h'36, (one byte): response to the number of erased blocks and addresses ? size (three bytes): the number of bytes that represents the number of blocks, block-start addresses, and block-last addresses. ? number of blocks (one byte): the number of erased blocks ? block start address (four bytes): start address of a block ? block last address (four bytes): last address of a block there are as many groups of data representing the start and last addre sses as there are areas. ? sum (one byte): checksum
rev. 2.00, 03/04, page 446 of 534 (j) programming unit inquiry the boot program will return the programming unit used to program data. command h'27 ? command, h'27, (one byte): inquiry regarding programming unit response h'37 size programming unit sum ? response, h'37, (one byte): response to programming unit inquiry ? size (one byte): the number of bytes that indicate the programming unit, which is fixed to 2 ? programming unit (two bytes): a unit for programming this is the unit for reception of programming. ? sum (one byte): checksum (k) new bit-rate selection the boot program will set a new bit rate and return the new bit rate. this selection should be sent after sending the clock mode selection command. command h'3f size bit rate input frequency number of multiplication ratios multiplication ratio 1 multiplication ratio 2 sum ? command, h'3f, (one byte): selection of new bit rate ? size (one byte): the number of bytes that represents the bit rate, input frequency, number of multiplication ratios, and multiplication ratio ? bit rate (two bytes): new bit rate one hundredth of the value (e.g. when the value is 19200 bps, it will be 192, which is h'00c0.) ? input frequency (two bytes): frequency of the clock input to the boot program this is valid to the hundredths place and represen ts the value in mhz mul tiplied by 100. (e.g. when the value is 20.00 mhz, it will be 2000, which is h'07d0.) ? number of multiplication ratios (one byte): the number of multiplication ratios to which the device can be set. ? multiplication ratio 1 (one byte): the value of multiplication or division ratios for the main operating frequency multiplication ratio (one byte): the value of the multiplication ratio (e.g. when the clock frequency is multiplied by four, the multiplication ratio will be h'04.) division ratio: the inverse of the division ratio, as a negative number (e.g. when the clock frequency is divided by two, the value of division ratio will be h'fe. h'fe = d'-2)
rev. 2.00, 03/04, page 447 of 534 ? multiplication ratio 2 (one byte): the value of multiplication or division ratios for the peripheral frequency multiplication ratio (one byte): the value of the multiplication ratio (e.g. when the clock frequency is multiplied by four, the multiplication ratio will be h'04.) (division ratio: the inverse of the division ratio, as a negative number (e.g. when the clock is divided by two, the value of division ratio will be h'fe. h'fe = d'-2) ? sum (one byte): checksum response h'06 ? response, h'06, (one byte): response to selection of a new bit rate when it is possible to set the bit rate, the response will be ack. error response h'bf error ? error response, h'bf, (one byte): error response to selection of new bit rate ? error: (one byte): error code h'11: sum checking error h'24: bit-rate selection error the rate is not available. h'25: error in input frequency this input frequency is not within the specified range. h'26: multiplication-ratio error the ratio does not match an available ratio. h'27: operating frequency error the frequency is not within the specified range. received data check: the methods for checking of r eceived data are listed below. 1. input frequency the received value of the input fr equency is checked to ensure th at it is within the range of minimum to maximum frequencies which matches the clock modes of the specified device. when the value is out of this range, an input-frequency error is generated. 2. multiplication ratio the received value of the multipli cation ratio or division ratio is checked to ensure that it matches the clock modes of the specified device. when the value is out of this range, an input- frequency error is generated. 3. operating frequency error operating frequency is calculated from the r eceived value of the input frequency and the multiplication or division ratio. the input frequency is input to the lsi and the lsi is operated at the operating frequency. the expression is given below. operating frequency = input frequency multiplication ratio, or operating frequency = input frequency division ratio
rev. 2.00, 03/04, page 448 of 534 the calculated operating frequency should be checked to ensure that it is within the range of minimum to maximum frequencies which are available with the clock modes of the specified device. when it is out of this range, an operating frequency error is generated. 4. bit rate to facilitate error checking, the value (n) of clock select (cks) in the serial mode register (smr), and the value (n) in the bit rate regi ster (brr), which are fo und from the peripheral operating clock frequency ( ) and bit rate (b), are used to calculate the error rate to ensure that it is less than 4%. if the error is more than 4%, a bit rate error is generated. the error is calculated using the following expression: error ( % ) = {[ ] ? 1} 100 (n + 1) b 64 2 (2 n ? 1) 10 6 when the new bit rate is selectable, the rate will be set in the register after sending ack in response. the host will send an ack with the new bit rate for confirmation and the boot program will response with that rate. confirmation h'06 ? confirmation, h'06, (one byte): confirmation of a new bit rate response h'06 ? response, h'06, (one byte): response to confirmation of a new bit rate the sequence of new bit-rate selection is shown in figure 14.24. host boot program setting a new bit rate h'06 (ack) waiting for one-bit period at the specified bit rate h'06 (ack) with the new bit rate h'06 (ack) with the new bit rate setting a new bit rate setting a new bit rate figure 14.24 new bit- rate selection sequence
rev. 2.00, 03/04, page 449 of 534 transition to programming/erasing state: the boot program will tran sfer the erasing program, and erase the user mats and user boot mats in th at order. on completion of this erasure, ack will be returned and will enter the programming/erasing state. the host should select the device code, clock mode, and new bit rate with device selection, clock- mode selection, and new bit-rate selection commands, and then send the command for the transition to programming/erasing st ate. these procedures should be carried out before sending of the programming selection command or program data. command h'40 ? command, h'40, (one byte): transition to programming/erasing state response h'06 ? response, h'06, (one byte): response to transition to programming/erasing state the boot program will send ack when the user mat and user boot mat have been erased by the transferred erasing program. error response h'c0 h'51 ? error response, h'c0, (one byte): error response for user boot mat blank check ? error code, h'51, (one byte): erasing error an error occurred and er asure was not completed. command error: a command error will occur when a command is undefined, the order of commands is incorrect, or a comma nd is unacceptable. issuing a clock-mode selection command before a device selection or an inquiry command after the transition to programming/erasing state command, are examples. error response h'80 h'xx ? error response, h'80, (one byte): command error ? command, h'xx, (one byte): received command command order: the order for commands in the inquiry selection state is shown below. 1. a supported device inquiry (h'20) should be made to inquire about the supported devices. 2. the device should be selected from among those described by the returned information and set with a device-selection (h'10) command. 3. a clock-mode inquiry (h'21) should be made to inquire about the supported clock modes. 4. the clock mode should be selected from among those described by the returned information and set. 5. after selection of the device and clock mode, inquiries for other required information should be made, such as the multiplication-ratio inquiry (h'22) or operating frequency inquiry (h'23), which are needed for a new bit-rate selection.
rev. 2.00, 03/04, page 450 of 534 6. a new bit rate should be selected with the new bit-rate selection (h'3f) command, according to the returned information on multiplication ratios and operating frequencies. 7. after selection of the device and clock mode, the information of the user boot mat and user mat should be made to inquire about the user boot mats information inquiry (h'24), user mats information inquiry (h'25), erased block information inquiry (h'26), and programming unit inquiry (h'27). 8. after making inquiries and selecting a new bit rate, issue the transition to programming/erasing state command (h'40). the boot program will then enter the programming/erasing state. programming/erasing state: a programming selection command makes the boot program select the programming method, a 128-byte programming command makes it program the memory with data, and an erasing selection command and bloc k erasing command make it erase the block. the programming/erasing commands are listed below. table 14.13 programming/erasing command command command name description h'42 user boot mat programming selection t ransfers the user boot mat programming program h'43 user mat programming selection transfers the user mat programming program h'50 128-byte programming programs 128 bytes of data h'48 erasing selection trans fers the erasing program h'58 block erasing erases a block of data h'52 memory read reads the contents of memory h'4a user boot mat sum check checks the checksum of the user boot mat h'4b user mat sum check checks the checksum of the user mat h'4c user boot mat blank check checks the blank data of the user boot mat h'4d user mat blank check checks the blank data of the user mat h'4c user boot mat blank check che cks whether the cont ents of the user boot mat are blank h'4d user mat blank check checks whether the content s of the user mat are blank h'4f boot program status inquiry i nquires into the boot program?s status
rev. 2.00, 03/04, page 451 of 534 ? programming programming is executed by a programming-selection command and a 128-byte programming command. firstly, the host should send the programming-selection command and select the programming method and programming mats. there are two programming selection commands, and selection is according to the ar ea and method for programming. 1. user boot mat programming selection 2. user mat programming selection after issuing the programming selection command, the host should send the 128-byte programming command. the 128-byte programming command that follows the selection command represents the data pr ogrammed according to the meth od specified by the selection command. when more than 128-byte data is programmed, 128-byte commands should repeatedly be executed. sending a 128-byte programming command with h'ffffffff as the address will stop the programming. on comp letion of programming, the boot program will wait for selection of programming or erasing. where the sequence of programming operations th at is executed includes programming with another method or of another mat, the procedure must be repeated from the programming selection command. the sequence for programming-selection and 128-byte programming commands is shown in figure 14.25. transfer of the programming program host boot program programming selection (h'42, h'43) ack programming 128-byte programming (address, data) ack 128-byte programming (h'ffffffff) ack repeat figure 14.25 programming sequence
rev. 2.00, 03/04, page 452 of 534 (a) user boot mat programming selection the boot program will transfer a programming program. the data is programmed to the user boot mats by the transferred programming program. command h'42 ? command, h'42, (one byte): user boot-program programming selection response h'06 ? response, h'06, (one byte): response to user boot-program programming selection when the programming program has been transferred, the boot program will return ack. error response h'c2 error ? error response : h'c2 (1 byte): error response to user boot mat programming selection ? error : (1 byte): error code h'54: selection processing error (transfer error occurs and processing is not completed) ? user-program programming selection the boot program will transfer a program for programming. the data is programmed to the user mats by the transferred program for programming. command h'43 ? command, h'43, (one byte): user-program programming selection response h'06 ? response, h'06, (one byte): response to user-program programming selection when the programming program has been transferred, the boot program will return ack. error response h'c3 error ? error response : h'c3 (1 byte): error response to user mat programming selection ? error : (1 byte): error code h'54: selection processing error (transfer erro r occurs and processing is not completed) (b) 128-byte programming the boot program will use the programming program transferred by the programming selection to program the user boot mats or user mats in response to 128-byte programming. command h'50 address data sum ? command, h'50, (one byte): 128-byte programming
rev. 2.00, 03/04, page 453 of 534 ? programming address (four bytes): start address for programming multiple of the size specified in response to the programming unit inquiry (i.e. h'00, h ' 01, h'00, h'00 : h'01000000) ? programming data (128 bytes): data to be programmed the size is specified in the response to the programming unit inquiry. ? sum (one byte): checksum response h'06 ? response, h'06, (one byte): response to 128-byte programming on completion of programming, the boot program will return ack. error response h'd0 error ? error response, h'd0, (one byte): error response for 128-byte programming ? error: (one byte): error code h'11: checksum error h'2a: address error h'53: programming error a programming error has occurred and programming cannot be continued. the specified address should match the unit for programming of data. fo r example, when the programming is in 128-byte units, the lower eight bits of the address should be h'00 or h'80. when there are less than 128 bytes of data to be programmed, the host should fill the rest with h'ff. sending the 128-byte programming command with the address of h'ffffffff will stop the programming operation. the boot program will interpret this as the end of the programming and wait for selection of programming or erasing. command h'50 address sum ? command, h'50, (one byte): 128-byte programming ? programming address (four bytes): end code is h'ff, h'ff, h'ff, h'ff. ? sum (one byte): checksum response h'06 ? response, h'06, (one byte): response to 128-byte programming on completion of programming, the boot program will return ack.
rev. 2.00, 03/04, page 454 of 534 error response h'd0 error ? error response, h'd0, (one byte): error response for 128-byte programming ? error: (one byte): error code h'11: checksum error h'2a: address error h'53: programming error an error has occurred in programming and programming cannot be continued. erasure: erasure is performed with the erasure selection and block erasure command. firstly, erasure is selected by the erasure selection command and th e boot program then erases the specified block. the command should be repeatedly executed if two or more blocks are to be erased. sending a block-erasure command from the host with the block number h'ff will stop the erasure operating. on completion of erasing, the boot program will wait for selection of programming or erasing. the sequences of the issuing of erasure selection commands and th e erasure of data are shown in figure 14.26. transfer of erasure program host boot program preparation for erasure (h'48) ack erasure erasure (erasure block number) erasure (h'ff) ack ack repeat figure 14.26 erasure sequence
rev. 2.00, 03/04, page 455 of 534 (a) erasure selection the boot program will transfer the erasure progra m. user mat data is er ased by the transferred erasure program. command h'48 ? command, h'48, (one byte): erasure selection response h'06 ? response, h'06, (one byte): response for erasure selection after the erasure program has been transferred, the boot program will return ack. error response h'c8 error ? error response, h'c8, (one byte): error response to erasure selection ? error: (one byte): error code h'54: selection processing error (transfer error occurs and processing is not completed) (b) block erasure the boot program will erase the c ontents of the specified block. command h'58 size block number sum ? command, h'58, (one byte): erasure ? size (one byte): the number of bytes th at represents the er asure block number this is fixed to 1. ? block number (one byte): number of the block to be erased ? sum (one byte): checksum response h'06 ? response, h'06, (one byte): response to erasure after erasure has been completed, the boot program will return ack. error response h'd8 error ? error response, h'd8, (one byte): response to erasure ? error (one byte): error code h'11: sum check error h'29: block number error block number is incorrect. h'51: erasure error an error has occurred during erasure. on receiving block number h ff, the boot program will stop erasure and wait for a selection command.
rev. 2.00, 03/04, page 456 of 534 command h'58 size block number sum ? command, h'58, (one byte): erasure ? size, (one byte): the number of bytes that represents the block number this is fixed to 1. ? block number (one byte): h'ff stop code for erasure ? sum (one byte): checksum response h'06 ? response, h'06, (one byte): response to end of erasure (ack) when erasure is to be performed after the block number h ff has been sent, the procedure should be executed from th e erasure selection command. memory read: the boot program will return the data in the specified address. command h'52 size area read address read size sum ? command: h'52 (1 byte): memory read ? size (1 byte): amount of data that represents th e area, read address, and read size (fixed at 9) ? area (1 byte) h'00: user boot mat h'01: user mat an address error occurs wh en the area setting is incorrect. ? read address (4 bytes): star t address to be read from ? read size (4 bytes): size of data to be read ? sum (1 byte): checksum response h'52 read size data sum ? response: h'52 (1 byte): response to memory read ? read size (4 bytes): size of data to be read ? data (n bytes): data for the read size from the read address ? sum (1 byte): checksum
rev. 2.00, 03/04, page 457 of 534 error response h'd2 error ? error response: h'd2 (1 byte): error response to memory read ? error: (1 byte): error code h'11: sum check error h'2a: address error the read address is not in the mat. h'2b: size error the read size exceeds the mat. user-boot program sum check: the boot program will return the byte-by-byte total of the contents of the bytes of the user-b oot program, as a four-byte value. command h'4a ? command, h'4a, (one byte): sum check for user-boot program response h'5a size checksum of user boot program sum ? response, h'5a, (one byte): response to the sum check of user-boot program ? size (one byte): the number of byt es that represents the checksum this is fixed to 4. ? checksum of user boot program (four bytes): checksum of user boot mats the total of the data is obtained in byte units. ? sum (one byte): sum check for data being transmitted user-program sum check: the boot program will return the byte-by-byte total of the contents of the bytes of the user program. command h'4b ? command, h'4b, (one byte): sum check for user program response h'5b size checksum of user program sum ? response, h'5b, (one byte): response to the sum check of the user program ? size (one byte): the number of byt es that represents the checksum this is fixed to 4. ? checksum of user boot program (four bytes): checksum of user mats the total of the data is obtained in byte units. ? sum (one byte): sum check for data being transmitted
rev. 2.00, 03/04, page 458 of 534 user boot mat blank check: the boot program will check whether or not all user boot mats are blank and return the result. command h'4c ? command, h'4c, (one byte): blank check for user boot mat response h'06 ? response, h'06, (one byte): response to the blank check of user boot mat if all user mats are blank (h'ff), th e boot program will return ack. error response h'cc h'52 ? error response, h'cc, (one byte): response to blank check for user boot mat ? error code, h'52, (one byte): erasure has not been completed. user mat blank check: the boot program will check whether or not all user mats are blank and return the result. command h ' 4d ? command, h'4d, (one byte): blank check for user mats response h'06 ? response, h'06, (one byte): response to the blank check for user boot mats if the contents of all user mats are blank (h ff), the boot program will return ack. error response h'cd h'52 ? error response, h'cd, (one byte): error response to the blank check of user mats. ? error code, h'52, (one byte): erasure has not been completed. boot program state inquiry: the boot program will return indications of its present state and error condition. this inquiry can be made in the inquiry/selection state or the programming/erasing state. command h'4f ? command, h'4f, (one byte): inquiry regarding boot program's state response h'5f size status error sum ? response, h'5f, (one byte): response to boot program state inquiry ? size (one byte): the number of bytes. this is fixed to 2. ? status (one byte): state of the boot program
rev. 2.00, 03/04, page 459 of 534 ? error (one byte): error status error = 0 indicates normal operation. error = 1 indicates error has occurred. ? sum (one byte): sum check table 14.14 status code code description h'11 device selection wait h'12 clock mode selection wait h'13 bit rate selection wait h'1f programming/erasing stat e transition wait (bit rate selection is completed) h'31 programming state for erasure h'3f programming/erasing selection wait (erasure is completed) h'4f programming data receive wait h'5f erasure block specification wait (erasure is completed)
rev. 2.00, 03/04, page 460 of 534 table 14.15 error code code description h'00 no error h'11 sum check error h'12 program size error h'21 device code mismatch error h'22 clock mode mismatch error h'24 bit rate selection error h'25 input frequency error h'26 multiplication ratio error h'27 operating frequency error h'29 block number error h'2a address error h'2b data length error h'51 erasure error h'52 erasure incomplete error h'53 programming error h'54 selection processing error h'80 command error h'ff bit-rate-adjustment confirmation error
rev. 2.00, 03/04, page 461 of 534 14.10 usage notes 1. the initial state of the renesas technology's product at its shipment is in the erased state. for the product whose revision of erasing is undefined, we recommend to execute automatic erasure for checking the initial state (erased state) and compensating. 2. for the prom programmer suitable for programmer mode in this lsi and its program version, refer to the instruction manual of the socket adapter. 3. if the socket, socket adapter, or product index does not match the specifications, too much current flows and the product may be damaged. 4. if a voltage higher than the rated voltage is applied, the product may be fatally damaged. use a prom programmer that supports the renesas technology's 256 kbytes flash memory on-chip mcu device at 3.3 v. do not set the programmer to hn28f101 or the programming voltage to 5.0 v. use only the specified so cket adapter. if other adapters are used, the product may be damaged. 5. do not remove the chip from the prom programmer nor input a reset signal during programming/erasing. as a high voltage is applied to the flash memory during programming/erasing, doing so may damage or destroy flash memory permanently. if reset is executed accidentally, reset must be releas ed after the reset input period of 100 s which is longer than normal. 6. the flash memory is not accessible until fkey is cleare d after programming/erasing completes. if this lsi is restarted by a reset immediately after programming/erasing has finished, secure the reset period (period of res = 0) of more than 100 s. though transition to the reset state or hardware stan dby state during programming/erasing is prohibited, if reset is executed accidentally, reset must be releas ed after the reset input period of 100 s which is longer than normal. 7. at powering on or off the vcc power supply, fix the res pin to low and set the flash memory to hardware protection state. this power on/off timing must also be satisfied at a power-off and power-on caused by a power failure and other factors. 8. program the area with 128-byte programming-unit blocks in on-board programming or programmer mode only once. perform programming in the state where the programming-unit block is fully erased. 9. when the chip is to be reprogrammed with the programmer after execution of programming or erasure in on-board programming mode, it is recommended that automatic programming is performed after execution of automatic erasure. 10. to write data or programs to the flash memory, data or programs must be allocated to addresses higher than that of the external in terrupt vector table (h'000040) and h?ff must be written to the areas that are reserved for the system in the exception ha ndling vector table.
rev. 2.00, 03/04, page 462 of 534 11. if data other than h'ff (four bytes) is written to the key code area (h'00003c to h'00003f) of flash memory, reading cannot be performed in prog rammer mode. (in this case, data is read as h'00. rewrite is possible after erasing the data.) for reading in programmer mode, make sure to write h'ff to the entire key code area. if data other than h'ff is to be written to the key code area in programmer mode, a verification error will occur unless a software countermeasure is taken for the prom programmer. 12. the programming program that includes the initialization routine and the erasing program that includes the initialization routine are each 2 kbytes or less. accordingly, when the cpu clock frequency is 10 mhz, the download for each program takes approximately 600 s at the maximum. 13. while an instruction in on-chip ram is being executed, the dmac can write to the sco bit in fccs that is used for a download request or fmats that is used for mat switching. make sure that these registers are not accidentally written to, otherwise an on-chip program may be downloaded and damage ram or a mat switchover may occur and the cpu get out of control. do not use dmac to program flash related registers. 14. a programming/erasing program for flash memory used in the conventional f-ztat h8s microcomputer which does not support download of the on-chip program by a sco transfer request cannot run in this lsi. be sure to download the on-chip program to execute programming/erasing of flash memory in this lsi. 15. unlike the conventional f-ztat h8s microcom puter, no countermeasures are available for a runaway by wdt during programming/erasing. prepare countermeasures (e.g. use of the periodic timer interrupts) for wdt with taking the programming/erasing time into consideration as required. 16. while writing 1 to the sco bit and downloading the internal programs, the wdt coutup operation stops.
rev. 2.00, 03/04, page 463 of 534 section 15 clock pulse generator this lsi has an on-chip clock pulse generator that generates the system clock ( extal pll circuit ( 2) oscillator system clock to pin internal cloc k to peripheral modules xtal figure 15.1 block diagra m of clock pulse generator the frequency can be multiplied by two by means of the pll circuit. 15.1 oscillator clock pulses can be supplied by connecting a crystal resonator, or by input of an external clock. 15.1.1 connecting crystal resonator a crystal resonator can be connected as shown in the example in figure 15 .2. select the damping resistance r d according to table 15.1. an at-cut parallel-resonance type should be used. when a crystal resonator is used, the range of usable frequencies is from 5 to 16.5 mhz and a crystal resonator with half frequency of the system clock (
rev. 2.00, 03/04, page 464 of 534 extal xtal r d c l2 c l1 c l1 = c l2 = 10 to 22 pf figure 15.2 connection of crystal resonator (example) table 15.1 damping resistance value frequency (mhz) 5 8 12 16.5 r d ( ? ) 425 200 0 0 xtal c l at-cut parallel-resonance type extal c 0 lr s figure 15.3 crystal reso nator equivalent circuit table 15.2 crystal resonator characteristics frequency (mhz) 5 8 12 16.5 r s max ( ? ) 110 80 60 50 c 0 max (pf) 7 7 7 7 15.1.2 external clock input an external clock signal can be input as shown in the examples in figure 15.4. if the xtal pin is left open, make sure that parasitic capacitance is no more than 10 pf. when the counter clock is input to the xtal pin, make sure that the external clock is held high in standby mode. table 15.3 shows the input conditions for the extern al clock. when an exte rnal clock is used, the range of usable frequencies is from 5 to 16.5 mhz and an external clock with half frequency of the system clock (
rev. 2.00, 03/04, page 465 of 534 extal xtal external clock input open (a) xtal pin left open extal xtal external clock input (b) counter clock input at xtal pin figure 15.4 external clock input (examples) table 15.3 external clock input conditions v cc = 3.0 v to 3.6 v test item symbol min. max. unit conditions external clock input low pulse width t exl 10 ? ns figure 15.5 external clock input high pulse width t exh 10 ? ns external clock rise time t exr ? 5 ns external clock fall time t exf ? 5 ns clock low pulse width t cl 0.4 0.6 t cyc figure 18.2 clock high pulse width t ch 0.4 0.6 t cyc t exh t exl t exr t exf v cc 0.5 extal figure 15.5 external clock input timing
rev. 2.00, 03/04, page 466 of 534 when the specified clock signal is input to the extal pin, an internal clock signal output is ensured after the external clock output stabilization delay time (t dext ) is passed. since the clock signal output is not ensured during the t dext period, the reset signal should be set to low and the reset state should be retained. table 15.4 shows the external clock output stabilization delay time and figure 15.6 shows the timing of the external clock output stabilization delay time. table 15.4 external clock output stabilization delay time conditions: vcc = 3.0 v to 3.6 v, vss = 0 v item symbol min. max. unit remark external clock output stabilization delay time t dext * 500 ? s figure 15.6 note: * t dext includes the res pulse width (t resw ). t dext * extal note: * t dext includes the pulse width (t resw ). (internal or external) v cc 2.7v v ih figure 15.6 timing of external clock output stabilization delay time 15.2 pll circuit the pll circuit has the function of multiplying the frequency of the clock from the oscillator by a factor of 2. therefore, a 16.5-mhz clock should be input to realize the inte rnal 33-mhz operation. the phase of the rising edge of th e internal clock is controlled so as to match that of the rising edge of the extal pin.
rev. 2.00, 03/04, page 467 of 534 15.3 usage notes 15.3.1 notes on resonator since various characteristics related to the resonato r are closely linked to the user's board design, thorough evaluation is necessary on the user's part, using the resonator connection examples shown in this section as a guide. as the parameters for the oscillation circuit will depend on the floating capacitance of the resonator and the user board, the parameters should be determined in consultation with the resonator ma nufacturer. the design must ensu re that a voltage exceeding the maximum rating is not applied to the resonator pin. 15.3.2 notes on board design when using the crystal resonator, place the crysta l resonator and its load capacitors as close as possible to the xtal and extal pins. other signal lines should be routed away from the oscillation circuit to prevent induction from interfering with correct oscillation. see figure 15.7. c l2 signal a signal b c l1 this lsi xtal extal avoid figure 15.7 note on board design for oscillation circuit 15.3.3 note on confirming the operation this lsi may oscillate itself on some khz frequency even if a crystal resonator is not connected to the extal pin or xtal pin, or the external clock is not input. therefore, make sure this lsi is working on the correct frequency before use.
rev. 2.00, 03/04, page 468 of 534
rev. 2.00, 03/04, page 469 of 534 section 16 power-down modes in addition to the normal program execution state, this lsi has power-down modes in which operation of the cpu and oscillator is halted and power consumption is reduced. low-power operation can be achieved by individually cont rolling the cpu, on-chip peripheral modules, and so on. this lsi's operating modes are high-speed mode and four power down modes: ? sleep mode ? module stop mode ? software standby mode ? hardware standby mode sleep mode is a cpu state and module stop mode is an on-chip peripheral function state. a combination of these modes can be set. after a reset, this lsi is in high-speed mode. table 16.1 shows the internal states of this lsi in each mode. figure 16.1 shows the mode transition diagram.
rev. 2.00, 03/04, page 470 of 534 table 16.1 operating modes and internal states of lsi operating state high-speed mode sleep mode module stop mode software standby mode hardware standby mode clock pulse generator functions functions functions halted halted instruction execution halted halted halted cpu register functions retained functions retained undefined nmi external interrupts irq0 to irq7 functions functions functions functions halted peripheral functions wdt functions functions functions halted (retained) halted (reset) tmr functions functions halted (retained) halted (retained) halted (reset) dmac functions functions functions halted (retained) halted (reset) sci functions functions halted (reset) halted (reset) halted (reset) usb2 functions functions halted (retained) halted (retained) halted (reset) ram functions functions functions retained retained i/o functions functions functions retained high impedance note: halted (retained) in the table means that in ternal register values are retained and internal operations are suspended. halted (reset) in the table means that intern al register values and internal states are initialized. in module stop mode, only modules for wh ich a stop setting has been made are halted (reset or retained).
rev. 2.00, 03/04, page 471 of 534 program-halted state program execution state high-speed mode (internal clock is pll circuit output clock) reset state pin = low pin = high pin = low ssby = 0 ssby = 1 pin = high : transition after exception handling : power- down mode sleep instruction any interrupt sleep instruction external interrupt * and susri interrupt note: * nmi, to ? from any state, a transition to hardware standby mode occurs when is driven low. from any state except hardware standby mode, a transition to the reset state occurs when is driven low. hardware standby mode sleep mode software standby mode figure 16.1 mode transitions
rev. 2.00, 03/04, page 472 of 534 16.1 register descriptions the registers relating to the power-down mode are shown below. ? standby control register (sbycr) ? module stop control registers h and l (mstpcrh, mstpcrl) 16.1.1 standby control register (sbycr) sbycr performs software standby mode control. bit bit name initial value r/w description 7 ssby 0 r/w software standby this bit specifies the transit ion mode after executing the sleep instruction 0: shifts to sleep mode after the sleep instruction is executed 1: shifts to software standby mode after the sleep instruction is executed this bit does not change when clearing the software standby mode by using external interrupts and shifting to normal operation. this bit should be written to 0 when clearing. 6 5 4 sts2 sts1 sts0 0 0 0 r/w r/w r/w standby timer select 2 to 0 these bits select the time the mcu waits for the clock to stabilize when software standby mode is cleared. make a selection according to the operating frequency so that the standby time is at least oscillation stabilization time. table 16.2 shows the relationship between setting values and number of wait states. with an external clock, any selection is possible. normally the minimum va lue is recommended. 3 to 0 ? all 0 r/w reserved the initial value should not be changed.
rev. 2.00, 03/04, page 473 of 534 16.1.2 module stop control regi sters h and l (mstpcrh, mstpcrl) mstpcr performs module stop mode control. setting a bit to 1, the corresponding module enters module stop mode, while clearing the bit to 0 clears the module stop mode. ? mstpcrh bit bit name initial value r/w module 7 ? 0 * 1 r/w ? 6 ? 0 * 1 r/w ? 5 ? 1 * 2 r/w ? 4 tmrckstp 1 r/w 8-bit timer (tmr) 3 ? 1 * 2 r/w ? 2 ? 1 * 2 r/w ? 1 ? 1 * 2 r/w ? 0 ? 1 * 2 r/w ? ? mstpcrl bit bit name initial value r/w module 7 scickstp 1 r/w serial communication interface (sci) 6 ? 1 * 2 r/w ? 5 ? 1 * 2 r/w ? 4 usbckstp 1 r/w universal serial bus interface 2 (usb2) 3 ? 1 * 2 r/w ? 2 ? 1 * 2 r/w ? 1 ? 1 * 2 r/w ? 0 ? 1 * 2 r/w ? note: * 1 this bit must not set to 1. * 2 these bits must not be cleared to 0.
rev. 2.00, 03/04, page 474 of 534 16.2 operation 16.2.1 sleep mode transition to sleep mode: when the sleep instruction is executed while the ssby bit in sbycr is set to 0, the cpu enters the sleep mode. in sleep mode, cpu operation stops but the contents of the cpu's internal registers are retained. other peripheral functions do not stop. exiting sleep mode: sleep mode is exited by any interrupt, or signals at the res , or stby pins. ? exiting sleep mode by interrupts when an interrupt occurs, sleep mode is exited and interrupt exception pr ocessing starts. sleep mode is not exited if the interrupt is disabled, or interrupts other than nmi are masked by the cpu. ? exiting sleep mode by res pin setting the res pin level low selects the reset state. after the stipulated reset input duration, driving the res pin high starts the cpu performing reset exception processing. ? exiting sleep mode by stby pin when the stby pin level is driven low, a transition is made to hardware standby mode. 16.2.2 software standby mode transition to software standby mode: if a sleep instruction is executed when the ssby bit in sbycr is set to 1, software standby mode is entered. in this mode, the cpu, on-chip peripheral functions, and oscillator all stop. however, the cont ents of the cpu's internal registers, ram data, and the states of on-chip peripheral functions other than the sci, and i/o ports, are retained. in this mode the oscillator stops, and therefore power consumption is significantly reduced. clearing software standby mode: software standby mode is cleared by an external interrupt (nmi pin, or pins irq0 to irq7), susri interrupt or by means of the res pin or stby pin. ? clearing with an interrupt when an nmi, irq0 to irq7 or susri interrupt request signal is input, clock oscillation starts, and after the elapse of the time set in bi ts sts2 to sts0 in sbycr, stable clocks are supplied to the entire lsi, software standby mode is cleared, and interrupt exception handling is started. when clearing software standby mode with an irq0 to irq7 or susri interrupt, set the corresponding enable bit to 1 and ensure that no interrupt with a higher priority than interrupts irq0 to irq7 or susri is generated. software standby mode cannot be cleared if the interrupt has been masked on the cpu side.
rev. 2.00, 03/04, page 475 of 534 ? clearing with the res pin when the res pin is driven low, clock oscillation is started. at the same time as clock oscillation starts, clocks are supplied to the entire lsi. note that the res pin must be held low until clock oscillation stabilizes. when the res pin goes high, the cpu begins reset exception handling. ? clearing with the stby pin when the stby pin is driven low, a transition is made to hardware standby mode. setting oscillation stabilization time after clearing software standby mode: bits sts2 to sts0 in sbycr should be set as described below. ? using a crystal resonator set bits sts2 to sts0 so that the standby time is more than the oscillation stabilization time. table 16.2 shows the standby times for operating frequencies and settings of bits sts2 to sts0. ? using an external clock a pll circuit stabilization time is necessary. refe r to table 16.2 to set the standby time. table 16.2 operating frequency and standby time sts2 sts1 sts0 standby time 10 mhz 20 mhz 33 mhz unit 0 0 0 8192 states 0.8 0.4 0.2 ms 1 16384 states 1.6 0.8 0.4 1 0 32768 states 3.2 1.6 0.9 1 65536 states 6.5 3.2 1.9 1 0 0 131072 states 13.1 6.5 3.9 1 262144 states 26.2 13.1 7.9 1 0 reserved ? ? ? ? 1 16 states * 1.6 0.8 0.4 s : recommended setting time note: * this setting must not be used in the flash memory version. software standby mode application example: figure 16.2 shows an example in which a transition is made to software standby mode at the falling edge on the nmi pin, and software standby mode is cleared at th e rising edge on the nmi pin. in this example, an nmi interr upt is accepted with the nmieg bit in syscr cleared to 0 (falling edge specification), then the nmieg bit is set to 1 (rising edge specification), the ssby bit is set to 1, and a sleep instruction is executed, cau sing a transition to software standby mode. software standby mode is then cleared at the rising edge on the nmi pin.
rev. 2.00, 03/04, page 476 of 534 oscillator nmi nmieg ssby nmi exception handling nmieg=1 ssby=1 sleep instruction software standby mode (power-down mode) oscillation stabilization time t osc2 nmi exception handling figure 16.2 software standby mode application example 16.2.3 hardware standby mode transition to hardware standby mode: when the stby pin is driven low, a transition is made to hardware standby mode from any mode. in hardware standby mode, all functions enter the reset state and stop operation, resulting in a significant reduction in power consumption. as long as the prescribed volt age is supplied, on-chip ram data is retained. i/o ports are set to the high-impedance state. in order to retain on-chip ram data, the rame bit in syscr should be cleared to 0 before driving the stby pin low. do not change the state of the mode pins ( md2 , md1) while this lsi is in hardware standby mode.
rev. 2.00, 03/04, page 477 of 534 clearing hardwa re standby mode: hardware standby mode is cleared by means of the stby pin and the res pin. when the stby pin is driven high while the res pin is low, the reset state is set and clock oscillation is started. ensure that the res pin is held low until the clock oscillator stabilizes (for details on the oscillation stabilization time, refer to table 16.2). when the res pin is subsequently driven high, a transition is made to the program execution state via the reset exception handling state. hardware standby mode timing: figure 16.3 shows an example of hardware standby mode timing. when the stby pin is driven low after the res pin has been driven low, a transition is made to hardware standby mode. hardware standby mode is cleared by driving the stby pin high, waiting for the oscillation stabilization time, then changing the res pin from low to high. oscillator oscillation stabilization time reset exception handling figure 16.3 hardware standby mode timing 16.2.4 module stop mode module stop mode can be set for individual on-chip peripheral modules. when the corresponding bit in mstpcr is set to 1, module operation stops at the end of the bus cycle and a transition is made to module stop mode. the cpu continues operating independently. when the corresponding bit is cleared to 0, modul e stop mode is cleared and the module starts operating at the end of the bus cycl e. in module stop mode, the in ternal states of modules other than the sci are retained. after reset clearance, all modules other than the dmac are in module stop mode. the module registers which are set in module stop mode cannot be read or written to.
rev. 2.00, 03/04, page 478 of 534 16.3 usage notes 16.3.1 i/o port status in software standby mode, i/o port states are reta ined. therefore, there is no reduction in current consumption for the output current when a high-level signal is output. 16.3.2 current consumption during oscillation stabilization standby period current consumption increases during the oscillation stabilization standby period. 16.3.3 on-chip peripheral module interrupts relevant interrupt operations cannot be performed in module stop mode. consequently, if module stop mode is entered when an interrupt has been requested, it will not be possible to clear the cpu interrupt source activation source. interrupts shou ld therefore be disabled before entering module stop mode. 16.3.4 writing to mstpcr mstpcr should only be written to by the cpu.
rev. 2.00, 03/04, page 479 of 534 section 17 list of registers this section gives information on the on-chip i/o register addresses, how the register bits are configured, and the register states in each operating mode. the information is given as shown below. 1. register addresses (address order) ? registers are listed from the lower allocation addresses. ? registers are classified by functional modules. ? the access size is indicated. 2. register bits ? bit configurations of the registers are described in the same order as the register addresses. ? reserved bits are indicated by ? in the bit name column. ? the bit number in the bit-name column indicates that the whol e register is allocated as a counter or for holding data. ? for the registers of 16 or 24 bits, the msb is described first. 3. register states in each operating mode ? register states are described in the sa me order as the register addresses. ? the register states described here are for the basic operating mode s. if there is a specific reset for an on-chip peripheral module, refer to th e section on that on-chip peripheral module.
rev. 2.00, 03/04, page 480 of 534 17.1 register addresses (address order) the data bus width indicates the numbers of bits by which the register is accessed. the number of access states indicates the number of states based on the sp ecified reference clock. register name abbreviation number of bits address module data width access states interrupt flag register 0 ifr0 32 h'fd00 usb2 32 2 interrupt select register 0 isr0 32 h'fd04 usb2 32 2 interrupt enable register 0 ier0 32 h'fd08 usb2 32 2 ep0o receive data size register epsz0o 32 h'fd0c usb2 32 2 ep1 receive data size register epsz1 32 h'fd10 usb2 32 2 ep0i data register epdr0i 32 h'fd14 usb2 32 2 ep0o data register epdr0o 32 h'fd18 usb2 32 2 ep0s data register epdr0s 32 h'fd1c usb2 32 2 ep1 data register epdr1 32 h'fd20 usb2 32 2 ep2 data register epdr2 32 h'fd30 usb2 32 2 ep3 data register 3 epdr3 32 h'fd40 usb2 32 2 data status register 0 dasts0 32 h'fd44 usb2 32 2 packet enable register 0i pkte0i 32 h'fd48 usb2 32 2 packet enable register 2 pkte2 32 h'fd4c usb2 32 2 packet enable register 3 pkte3 32 h'fd50 usb2 32 2 fifo clear register 0 fclr0 32 h'fd54 usb2 32 2 endpoint stall register 0 epstl0 32 h'fd58 usb2 32 2 dma setting register dma0 32 h'fd5c usb2 32 2 control register ctrl 32 h'fd60 usb2 32 2 standby control register sbycr 8 h'fe14 system 8 2 module stop control register h mstpcrh 8 h'fe16 system 8 2 module stop control register l mstpcrl 8 h'fe17 system 8 2 system control register syscr 8 h'fe1c system 8 2 mode control register mdcr 8 h'fe1d system 8 2 usb suspend status register usbsusp 8 h'fe1e usb2 8 2 access control register acscr 8 h'fe20 bsc 16 2 cs assertion period control register csacr 8 h'fe21 bsc 16 2
rev. 2.00, 03/04, page 481 of 534 register name abbreviation number of bits address module data width access states wait control register wtcr 16 h'fe22 bsc 16 2 bus control register bcr 16 h'fe24 bsc 16 2 read strobe timing control register rdncr 8 h'fe26 bsc 16 2 ram emulation register ramer 8 h'fe27 flash 16 2 dram control register dramcr 16 h'fe28 bsc 16 2 dram access control register draccr 8 h'fe2a bsc 16 2 refresh control register refcr 16 h'fe2c bsc 16 2 refresh timer counter rtcnt 8 h'fe2e bsc 16 2 refresh time constant regist er rtcor 8 h'fe2f bsc 16 2 timer control/status register tcsr 8 h'fe70 wdt 16 2 timer counter tcnt 8 h'fe71 wdt 16 2 flash code control/status register fccs 8 h'fe88 flash 8 2 flash program code select register fpcs 8 h'fe89 flash 8 2 flash erase code select register fecs 8 h'fe8a flash 8 2 flash key code register fkey 8 h'fe8c flash 8 2 flash mat select register fmats 8 h'fe8d flash 8 2 flash transfer destination address register ftdar 8 h'fe8e flash 8 2 dma source address register_0 dmsar_0 32 h'feb0 dmac_0 16 2 dma destination address register_0 dmdar_0 32 h'feb4 dmac_0 16 2 dma transfer count register_0 dmtcr_0 32 h'feb8 dmac_0 16 2 dma mode control register_0 dmmdr_0 16 h'febc dmac_0 16 2 dma address control register_0 dmacr_0 16 h'febe dmac_0 16 2 dma source address register_1 dmsar_1 32 h'fec0 dmac_1 16 2 dma destination address register_1 dmdar_1 32 h'fec4 dmac_1 16 2 dma transfer count register_1 dmtcr_1 32 h'fec8 dmac_1 16 2 dma mode control register_1 dmmdr_1 16 h'fecc dmac_1 16 2 dma address control register_1 dmacr_1 16 h'fece dmac_1 16 2
rev. 2.00, 03/04, page 482 of 534 register name abbreviation number of bits address module data width access states dma source address register_2 dmsar_2 32 h'fed0 dmac_2 16 2 dma destination address register_2 dmdar_2 32 h'fed4 dmac_2 16 2 dma transfer count register_2 dmtcr_2 32 h'fed8 dmac_2 16 2 dma mode control register_2 dmmdr_2 16 h'fedc dmac_2 16 2 dma address control register_2 dmacr_2 16 h'fede dmac_2 16 2 dma source address register_3 dmsar_3 32 h'fee0 dmac_3 16 2 dma destination address register_3 dmdar_3 32 h'fee4 dmac_3 16 2 dma transfer count register_3 dmtcr_3 32 h'fee8 dmac_3 16 2 dma mode control register_3 dmmdr_3 16 h'feec dmac_3 16 2 dma address control register_3 dmacr_3 16 h'feee dmac_3 16 2 usb transfer control register ustcr 16 h'fef0 dmac 16 2 irq enable register ier 8 h'ff46 int 8 2 interrupt control register a icra 8 h'ff48 int 8 2 interrupt control register b icrb 8 h'ff49 int 8 2 interrupt control register c icrc 8 h'ff4a int 8 2 irq status register isr 8 h'ff4b int 8 2 irq sense control register h iscrh 8 h'ff4c int 8 2 irq sense control register l iscrl 8 h'ff4d int 8 2 address break control register abrkcr 8 h'ff54 int 8 2 break address register a pbara 8 h'ff55 int 8 2 break address register b pbarb 8 h'ff56 int 8 2 break address register c pbarc 8 h'ff57 int 8 2 irq sense port select regist er issr 8 h'ff5d port 8 2 port function control register 1 pfcr1 8 h'ff60 port 8 2 port function control register 3 pfcr3 8 h'ff62 port 8 2 port 1 data direction regist er p1ddr 8 h'ff70 port 8 2 port 2 data direction regist er p2ddr 8 h'ff71 port 8 2 port 3 data direction regist er p3ddr 8 h'ff72 port 8 2 port 4 data direction regist er p4ddr 8 h'ff73 port 8 2 port 5 data direction regist er p5ddr 8 h'ff74 port 8 2 port 6 data direction regist er p6ddr 8 h'ff75 port 8 2 port 7 data direction regist er p7ddr 8 h'ff76 port 8 2
rev. 2.00, 03/04, page 483 of 534 register name abbreviation number of bits address module data width access states port 8 data direction regist er p8ddr 8 h'ff77 port 8 2 port 9 data direction regist er p9ddr 8 h'ff78 port 8 2 port a data direction regist er paddr 8 h'ff79 port 8 2 serial mode register smr 8 h'ff88 sci 8 2 bit rate register brr 8 h'ff89 sci 8 2 serial control register scr 8 h'ff8a sci 8 2 transmit data register tdr 8 h'ff8b sci 8 2 serial status register ssr 8 h'ff8c sci 8 2 receive data register rdr 8 h'ff8d sci 8 2 port 1 register port 1 8 h'ffc0 port 8 2 port 2 register port 2 8 h'ffc1 port 8 2 port 3 register port 3 8 h'ffc2 port 8 2 port 4 register port 4 8 h'ffc3 port 8 2 port 5 register port 5 8 h'ffc4 port 8 2 port 6 register port 6 8 h'ffc5 port 8 2 port 7 register port 7 8 h'ffc6 port 8 2 port 8 register port 8 8 h'ffc7 port 8 2 port 9 register port 9 8 h'ffc8 port 8 2 port a register port a 8 h'ffc9 port 8 2 port 1 data register p1dr 8 h'ffd0 port 8 2 port 2 data register p2dr 8 h'ffd1 port 8 2 port 3 data register p3dr 8 h'ffd2 port 8 2 port 4 data register p4dr 8 h'ffd3 port 8 2 port 5 data register p5dr 8 h'ffd4 port 8 2 port 6 data register p6dr 8 h'ffd5 port 8 2 port 7 data register p7dr 8 h'ffd6 port 8 2 port 8 data register p8dr 8 h'ffd7 port 8 2 port 9 data register p9dr 8 h'ffd8 port 8 2 port a data register padr 8 h'ffd9 port 8 2 timer control register 0 tcr_0 8 h'ffe0 tmr_0 16 2 timer control register 1 tcr_1 8 h'ffe1 tmr_1 16 2 timer control/status register 0 tcsr_0 8 h'ffe2 tmr_0 16 2 timer control/status register 1 tcsr1 8 h'ffe3 tmr_1 16 2
rev. 2.00, 03/04, page 484 of 534 register name abbreviation number of bits address module data width access states time constant register a0 tcora_0 8 h'ffe4 tmr_0 16 2 time constant register a1 tcora_1 8 h'ffe5 tmr_1 16 2 time constant register b0 tcorb_0 8 h'ffe6 tmr_0 16 2 time constant register b1 tcorb_1 8 h'ffe7 tmr_1 16 2 timer counter 0 tcnt_0 8 h'ffe8 tmr_0 16 2 timer counter 1 tcnt1 8 h'ffe9 tmr_1 16 2
rev. 2.00, 03/04, page 485 of 534 17.2 register bits register bit names of the on-chip peripheral modules are described below. each line covers eight bits, and 16-bit and 32-bit re gisters are shown as 2 or 4 lines, respectively. register abbreviation bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 module ifr0 ? ? ? ? ? modemn 1 modemn0 modef usb2 ? ? ? ? ? ? vbusmn vbusf ? ? ? ? ? ? ep3tr ep3ts brst ep2tr ep2empt y ep1full setupt s ep0ots ep0itr ep0its isr0 ? ? ? ? ? ? ? modef ? ? ? ? ? ? ? vbusf ? ? ? ? ? ? ep3tr ep3ts brst ep2tr ep2empt y ep1full setupt s ep0ots ep0itr ep0its ier0 ? ? ? ? ? ? ? modef ? ? ? ? ? ? ? vbusf ? ? ? ? ? ? ep3tr ep3ts brst ep2tr ep2empt y ep1full setupt s ep0ots ep0itr ep0its epsz0o d31 d30 d29 d28 d27 d26 d25 d24 d23 d22 d21 d20 d19 d18 d17 d16 d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 epsz1 d31 d30 d29 d28 d27 d26 d25 d24 d23 d22 d21 d20 d19 d18 d17 d16 d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 epdr0i d31 d30 d29 d28 d27 d26 d25 d24 d23 d22 d21 d20 d19 d18 d17 d16 d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 epdr0o d31 d30 d29 d28 d27 d26 d25 d24 d23 d22 d21 d20 d19 d18 d17 d16 d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0
rev. 2.00, 03/04, page 486 of 534 register abbreviation bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 module epdr0s d31 d30 d29 d28 d27 d26 d25 d24 usb2 d23 d22 d21 d20 d19 d18 d17 d16 d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 epdr1 d31 d30 d29 d28 d27 d26 d25 d24 d23 d22 d21 d20 d19 d18 d17 d16 d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 epdr2 d31 d30 d29 d28 d27 d26 d25 d24 d23 d22 d21 d20 d19 d18 d17 d16 d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 epdr3 d31 d30 d29 d28 d27 d26 d25 d24 d23 d22 d21 d20 d19 d18 d17 d16 d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 dasts0 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ep3de ep2de ? ? ? ep0ide pkte0i d31 d30 d29 d28 d27 d26 d25 d24 d23 d22 d21 d20 d19 d18 d17 d16 d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 pkte2 d31 d30 d29 d28 d27 d26 d25 d24 d23 d22 d21 d20 d19 d18 d17 d16 d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 pkte3 d31 d30 d29 d28 d27 d26 d25 d24 d23 d22 d21 d20 d19 d18 d17 d16 d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0
rev. 2.00, 03/04, page 487 of 534 register abbreviation bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 module fclr0 ? ? ? ? ? ? ? ? usb2 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ep3clr ep2clr ep1clr ? ? ep0oclr ep0iclr epstl0 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ep3stl ep2stl ep1stl ep0stl dma0 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ep2dmae ep1dmae ctrl ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? asce pullup e sbycr ssby sts2 sts1 sts0 ? ? ? ? system mstpcrh ? ? ? tmrckstp ? ? ? ? mstpcrl scickstp ? ? usbckstp ? ? ? ? syscr ? ? intm1 intm0 xrst nmieg ? rame mdcr expe ? ? ? ? mds2 mds1 mds0 usbsusp ususmoni ususfg ususfg e ususou t ? ? ? ? usb2 acscr abw3 abw2 abw1 abw0 ast3 ast2 ast1 ast0 bsc csacr csxh3 csxh2 csxh1 csxh0 csxt3 csxt2 csxt1 csxt0 wtcr ? w32 w31 w30 ? w22 w21 w20 ? w12 w11 w10 ? w02 w01 w00 bcr ? ? ? ? ? ? ? wdbe ? ? ? ? idle1 idle0 idlc1 idlc0 rdncr rdn3 rdn2 rdn1 rdn0 ? ? ? ? ramer ? ? ? ? rams ram2 ram1 ram0 flash dramcr ? rast ? cast ? ? ? dset bsc be rcdm dds ? ? mxc2 mxc1 mxc0 draccr ? ? tpc1 tpc0 ? ? rcd1 rcd0
rev. 2.00, 03/04, page 488 of 534 register abbreviation bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 module refcr cmf cmie rcw1 rcw0 ? rtck2 rtck1 rtck0 bsc rfshe ? rlw1 rlw0 slfrf tpcs2 tpcs1 tpcs0 rtcnt bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 rtcor bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 tcsr ovf wt/ it tme ? rst/ n m i cks2 cks1 cks0 wdt tcnt bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 fccs fwe ? ? fler weinte ? ? sco flash fpcs ? ? ? ppvd ? ? ? ppvs fecs ? ? ? ? ? ? ? epvb fkey k7 k6 k5 k4 k3 k2 k1 k0 fmats ms7 ms6 ms5 ms4 ms3 ms2 ms1 ms0 ftdar tder tda6 tda5 tda4 tda3 tda2 tda1 tda0 dmsar_0 ? ? ? ? ? ? ? ? dmac_0 bit23 bit22 bit21 bit20 bit19 bit18 bit17 bit16 bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 dmdar_0 ? ? ? ? ? ? bit25 bit24 bit23 bit22 bit21 bit20 bit19 bit18 bit17 bit16 bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 dmtcr_0 ? ? ? ? ? ? ? ? bit23 bit22 bit21 bit20 bit19 bit18 bit17 bit16 bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 dmmdr_0 da bef drake tende dreqs ams mds1 mds0 die irf tceie sdir dtsize ? lwsize ? dmacr_0 sat1 sat0 sarie sara4 sara3 sara2 sara1 sara0 dat1 dat0 darie dara4 dara3 dara2 dara1 dara0 dmsar_1 ? ? ? ? ? ? ? ? dmac_1 bit23 bit22 bit21 bit20 bit19 bit18 bit17 bit16 bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0
rev. 2.00, 03/04, page 489 of 534 register abbreviation bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 module dmdar_1 ? ? ? ? ? ? ? ? dmac_1 bit23 bit22 bit21 bit20 bit19 bit18 bit17 bit16 bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 dmtcr_1 ? ? ? ? ? ? ? ? bit23 bit22 bit21 bit20 bit19 bit18 bit17 bit16 bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 dmmdr_1 da bef drake tende dreqs ams mds1 mds0 die irf tceie sdir dtsize ? lwsize ? dmacr_1 sat1 sat0 sarie sara4 sara3 sara2 sara1 sara0 dat1 dat0 darie dara4 dara3 dara2 dara1 dara0 dmsar_2 ? ? ? ? ? ? ? ? dmac_2 bit23 bit22 bit21 bit20 bit19 bit18 bit17 bit16 bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 dmdar_2 ? ? ? ? ? ? bit25 bit24 bit23 bit22 bit21 bit20 bit19 bit18 bit17 bit16 bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 dmtcr_2 ? ? ? ? ? ? ? ? bit23 bit22 bit21 bit20 bit19 bit18 bit17 bit16 bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 dmmdr_2 da bef drake tende dreqs ams mds1 mds0 die irf tceie sdir dtsize ? lwsize ? dmacr_2 sat1 sat0 sarie sara4 sara3 sara2 sara1 sara0 dat1 dat0 darie dara4 dara3 dara2 dara1 dara0 dmsar_3 ? ? ? ? ? ? ? ? dmac_3 bit23 bit22 bit21 bit20 bit19 bit18 bit17 bit16 bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0
rev. 2.00, 03/04, page 490 of 534 register abbreviation bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 module dmdar_3 ? ? ? ? ? ? bit25 bit24 dmac_3 bit23 bit22 bit21 bit20 bit19 bit18 bit17 bit16 bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 dmtcr_3 ? ? ? ? ? ? ? ? bit23 bit22 bit21 bit20 bit19 bit18 bit17 bit16 bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 dmmdr_3 da bef drake tende dreqs ams mds1 mds0 die irf tceie sdir dtsize ? lwsize ? dmacr_3 sat1 sat0 sarie sara4 sara3 sara2 sara1 sara0 dat1 dat0 darie dara4 dara3 dara2 dara1 dara0 ustcr ep1dmae urchs1urchs0 ? ep2dmae uwchs1 uwchs0 ? dmac ? ? ? ? ? ? ? ? ier irq7e irq6e irq5e irq4e irq3e irq2e ir q1e irq0e int icra icra7 icra6 icra5 icra 4 icra3 icra2 icra1 icra0 icrb icrb7 icrb6 icrb5 icrb 4 icrb3 icrb2 icrb1 icrb0 icrc icrc7 icrc6 icrc5 icrc4 icrc3 icrc2 icrc1 icrc0 isr irq7f irq6f ir q5f irq4f irq3f ir q2f irq1f irq0f iscrh irq7scb irq7sca irq6scb irq6sca irq5scb irq5sca irq4scb irq4sca iscrl irq3scb irq3sca irq2scb irq2sca irq1scb irq1sca irq0scb irq0sca abrkcr cmf ? ? ? ? ? ? bie pbara a23 a22 a21 a20 a19 a18 a17 a16 pbarb a15 a14 a13 a12 a11 a10 a9 a8 pbarc a7 a6 a5 a4 a3 a2 a1 ? issr iss7 iss6 iss5 iss4 iss3 iss2 iss1 iss0 port pfcr1 ? cs1e cs2e cs3e ckoe aloe amoe ahoe pfcr3 susrif susrie ? ? ? ? ? usbswrs t p1ddr p17ddr p16ddr p15ddr p14ddr p13ddr p12ddr p11ddr p10ddr p2ddr p27ddr p26ddr p25ddr p24ddr p23ddr p22ddr p21ddr p20ddr p3ddr p37ddr p36ddr p35ddr p34ddr p33ddr p32ddr p31ddr p30ddr p4ddr p47ddr p46ddr p45ddr p44ddr p43ddr p42ddr p41ddr p40ddr p5ddr p57ddr p56ddr p55ddr p54ddr p53ddr p52ddr p51ddr p50ddr p6ddr p67ddr p66ddr p65ddr p64ddr p63ddr p62ddr p61ddr p60ddr
rev. 2.00, 03/04, page 491 of 534 register abbreviation bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 module p7ddr p77ddr p76ddr p75ddr p74ddr p73ddr p72ddr p71ddr p70ddr port p8ddr p87ddr p86ddr p85ddr p84ddr p83ddr p82ddr p81ddr p80ddr p9ddr p97ddr p96ddr p95ddr p94ddr p93ddr p92ddr p91ddr p90ddr paddr ? ? ? ? pa3dd r pa2dd r pa1dd r pa0dd r smr c/ a chr pe o/ e stop ? cks1 cks0 sci brr bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 scr tie rie te re ? teie cke1 cke0 tdr bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 ssr tdre rdrf orer fer per tend ? ? rdr bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 port1 p17 p16 p15 p14 p13 p12 p11 p10 port port2 p27 p26 p25 p 24 p23 p22 p21 p20 port3 p37 p36 p35 p 34 p33 p32 p31 p30 port4 p47 p46 p45 p 44 p43 p42 p41 p40 port5 p57 p56 p55 p 54 p53 p52 p51 p50 port6 p67 p66 p65 p 64 p63 p62 p61 p60 port7 p77 p76 p75 p 74 p73 p72 p71 p70 port8 p87 p86 p85 p 84 p83 p82 p81 p80 port9 p97 p96 p95 p 94 p93 p92 p91 p90 porta rxdmon ? ? ? pa3 pa2 pa1 pa0 p1dr p17dr p16dr p15dr p14dr p13dr p12dr p11dr p10dr p2dr p27dr p26dr p25dr p24dr p23dr p22dr p21dr p20dr p3dr p37dr p36dr p35dr p34dr p33dr p32dr p31dr p30dr p4dr p47dr p46dr p45dr p44dr p43dr p42dr p41dr p40dr p5dr p57dr p56dr p55dr p54dr p53dr p52dr p51dr p50dr p6dr p67dr p66dr p65dr p64dr p63dr p62dr p61dr p60dr p7dr p77dr p76dr p75dr p74dr p73dr p72dr p71dr p70dr p8dr p87dr p86dr p85dr p84dr p83dr p82dr p81dr p80dr p9dr p97dr p96dr p95dr p94dr p93dr p92dr p91dr p90dr padr ? ? ? ? pa3dr pa2dr pa1dr pa0dr tcr_0 cmieb cmiea ovie cclr1 cclr0 cks2 cks1 cks0 tmr_0 tcr_1 cmieb cmiea ovie cclr1 cclr0 cks2 cks1 cks0 tmr_1 tcsr_0 cmfb cmfa ovf ? os3 os2 os1 os0 tmr_0
rev. 2.00, 03/04, page 492 of 534 register abbreviation bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 module tcsr1 cmfb cmfa ovf ? os3 os2 os1 os0 tmr_1 tcora_0 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 tmr_0 tcora_1 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 tmr_1 tcorb_0 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 tmr_0 tcorb_1 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 tmr_1 tcnt_0 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 tmr_0 tcnt1 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 tmr_1
rev. 2.00, 03/04, page 493 of 534 17.3 register states in each operating mode register abbreviation power-on reset normal operation sleep module stop software standby hardware standby module ifr0 initialized ? ? ? ? initialized usb2 isr0 initialized ? ? ? ? initialized ier0 initialized ? ? ? ? initialized epsz0o initialized ? ? ? ? initialized epsz1 initialized ? ? ? ? initialized epdr0i initialized ? ? ? ? initialized epdr0o initialized ? ? ? ? initialized epdr0s initialized ? ? ? ? initialized epdr1 initialized ? ? ? ? initialized epdr2 initialized ? ? ? ? initialized epdr3 initialized ? ? ? ? initialized dasts0 initialized ? ? ? ? initialized pkte0i initialized ? ? ? ? initialized pkte2 initialized ? ? ? ? initialized pkte3 initialized ? ? ? ? initialized fclr0 initialized ? ? ? ? initialized epstl0 initialized ? ? ? ? initialized dma0 initialized ? ? ? ? initialized ctrl initialized ? ? ? ? initialized sbycr initialized ? ? ? ? initialized system mstpcrh initialized ? ? ? ? initialized mstpcrl initialized ? ? ? ? initialized syscr initialized ? ? ? ? initialized mdcr initialized ? ? ? ? initialized usbsusp initialized ? ? ? ? initialized usb2 acscr initialized ? ? ? ? initialized bsc csacr initialized ? ? ? ? initialized wtcr initialized ? ? ? ? initialized bcr initialized ? ? ? ? initialized rdncr initialized ? ? ? ? initialized ramer initialized ? ? ? ? initialized
rev. 2.00, 03/04, page 494 of 534 register abbreviation power-on reset normal operation sleep module stop software standby hardware standby module dramcr initialized ? ? ? ? initialized bsc draccr initialized ? ? ? ? initialized refcr initialized ? ? ? ? initialized rtcnt initialized ? ? ? ? initialized rtcor initialized ? ? ? ? initialized tcsr initialized ? ? ? ? initialized wdt tcnt initialized ? ? ? ? initialized fccs initialized ? ? ? ? initialized flash fpcs initialized ? ? ? ? initialized fecs initialized ? ? ? ? initialized fkey initialized ? ? ? ? initialized fmats initialized ? ? ? ? initialized ftdar initialized ? ? ? ? initialized dmsar_0 initialized ? ? ? ? initialized dmac_0 dmdar_0 initialized ? ? ? ? initialized dmtcr_0 initialized ? ? ? ? initialized dmmdr_0 initialized ? ? ? ? initialized dmacr_0 initialized ? ? ? ? initialized dmsar_1 initialized ? ? ? ? initialized dmac_1 dmdar_1 initialized ? ? ? ? initialized dmtcr_1 initialized ? ? ? ? initialized dmmdr_1 initialized ? ? ? ? initialized dmacr_1 initialized ? ? ? ? initialized dmsar_2 initialized ? ? ? ? initialized dmac_2 dmdar_2 initialized ? ? ? ? initialized dmtcr_2 initialized ? ? ? ? initialized dmmdr_2 initialized ? ? ? ? initialized dmacr_2 initialized ? ? ? ? initialized dmsar_3 initialized ? ? ? ? initialized dmac_3 dmdar_3 initialized ? ? ? ? initialized dmtcr_3 initialized ? ? ? ? initialized dmmdr_3 initialized ? ? ? ? initialized dmacr_3 initialized ? ? ? ? initialized
rev. 2.00, 03/04, page 495 of 534 register abbreviation power-on reset normal operation sleep module stop software standby hardware standby module ustcr initialized ? ? ? ? initialized dmac ier initialized ? ? ? ? initialized int icrc initialized ? ? ? ? initialized icrb initialized ? ? ? ? initialized icra initialized ? ? ? ? initialized isr initialized ? ? ? ? initialized iscrh initialized ? ? ? ? initialized iscrl initialized ? ? ? ? initialized abrkcr initialized ? ? ? ? initialized pbara initialized ? ? ? ? initialized pbarb initialized ? ? ? ? initialized pbarc initialized ? ? ? ? initialized issr initialized ? ? ? ? initialized pfcr1 initialized ? ? ? ? initialized port pfcr3 initialized ? ? ? ? initialized p1ddr initialized ? ? ? ? initialized p2ddr initialized ? ? ? ? initialized p3ddr initialized ? ? ? ? initialized p4ddr initialized ? ? ? ? initialized p5ddr initialized ? ? ? ? initialized p6ddr initialized ? ? ? ? initialized p7ddr initialized ? ? ? ? initialized p8ddr initialized ? ? ? ? initialized p9ddr initialized ? ? ? ? initialized paddr initialized ? ? ? ? initialized smr initialized ? ? ? ? initialized sci brr initialized ? ? ? ? initialized scr initialized ? ? ? ? initialized tdr initialized ? ? initialized initialized initialized ssr initialized ? ? initialized initialized initialized rdr initialized ? ? initialized initialized initialized port1 ? ? ? ? ? ? port port2 ? ? ? ? ? ?
rev. 2.00, 03/04, page 496 of 534 register abbreviation power-on reset normal operation sleep module stop software standby hardware standby module port3 ? ? ? ? ? ? port port4 ? ? ? ? ? ? port5 ? ? ? ? ? ? port6 ? ? ? ? ? ? port7 ? ? ? ? ? ? port8 ? ? ? ? ? ? port9 ? ? ? ? ? ? porta ? ? ? ? ? ? p1dr initialized ? ? ? ? initialized p2dr initialized ? ? ? ? initialized p3dr initialized ? ? ? ? initialized p4dr initialized ? ? ? ? initialized p5dr initialized ? ? ? ? initialized p6dr initialized ? ? ? ? initialized p7dr initialized ? ? ? ? initialized p8dr initialized ? ? ? ? initialized p9dr initialized ? ? ? ? initialized padr initialized ? ? ? ? initialized tcr_0 initialized ? ? ? ? initialized tmr_0 tcr_1 initialized ? ? ? ? initialized tmr_1 tcsr_0 initialized ? ? ? ? initialized tmr_0 tcsr_1 initialized ? ? ? ? initialized tmr_1 tcora_0 initialized ? ? ? ? initialized tmr_0 tcora_1 initialized ? ? ? ? initialized tmr_1 tcorb_0 initialized ? ? ? ? initialized tmr_0 tcorb_1 initialized ? ? ? ? initialized tmr_1 tcnt_0 initialized ? ? ? ? initialized tmr_0 tcnt_1 initialized ? ? ? ? initialized tmr_1 note: ? is not initialized.
rev. 2.00, 03/04, page 497 of 534 section 18 electrical characteristics 18.1 absolute maximum ratings table 18.1 lists the absolute maximum ratings. table 18.1 absolute maximum ratings item symbol value unit power supply voltage v cc * ? 0.3 to + 4.3 v input voltage v in ? 0.3 to v cc + 0.3 v program voltage (fwe) v in ? 0.3 to v cc + 0.3 v operating temperature t opr regular specifications: ? 20 to + 75 c wide-range specifications: ? 40 to + 85 c operating temperature (flashmemory programing/erasure) t opr 0 to + 75 c storage temperature t stg ? 55 to + 125 c caution: permanent damage to the lsi may resu lt if absolute maximum ratings are exceeded. notes: * do not apply the power supply voltage to the vcl pin. if applied, permanent damage to the lsi may result. connect the external capacitor between this pin and gnd.
rev. 2.00, 03/04, page 498 of 534 18.2 dc characteristics table 18.2 dc characteristics (1) conditions: v cc = 3.0 v to 3.6 v, v ss = 0 v item symbol min. typ. max. unit test conditions vt ? v cc 0.2 ? ? v vt + ? ? v cc 0.7 v schmitt trigger input voltage p34 * 1 , p35 * 1 , p52 * 1 , p53 * 1 , p56 * 1 , p57 * 1 , port 7 * 1 , pa0 * 1 , pa1 * 1 vt + ? vt ? v cc 0.05 ? ? v input high voltage stby , md2 , md1 v ih v cc 0.9 ? v cc + 0.3 v res , nmi, fwe v cc 0.9 ? v cc + 0.3 v extal v cc 0.7 ? v cc + 0.3 v port 1 to port 9, port a * 2 2.2 ? v cc + 0.3 v input low voltage res , stby , md2 , md1, fwe v il ? 0.3 ? v cc 0.1 v nmi, extal ? 0.3 ? v cc 0.2 v port 1 to ports 9, port a * 2 ? 0.3 ? v cc 0.2 v output high all output pins v oh v cc ? 0.5 ? ? v i oh = ? 200 a voltage v cc ? 1.0 ? ? v i oh = ? 1 ma output low voltage all output pins v ol ? ? 0.4 v i ol = 1.6 ma res | l in | ? ? 10.0 a input leakage current stby , nmi, md2 , md1, fwe ? ? 1.0 a v in = 0.5 to v cc - 0.5 v notes: 1. when used as irq0 to irq7 . 2. when used as other than irq0 to irq7 .
rev. 2.00, 03/04, page 499 of 534 table 18.3 dc characteristics (2) conditions: v cc = 3.0 v to 3.6 v, v ss = 0 v item symbol min. typ. max. unit test conditions three-state leakage current (off state) port 1 to port 9, port a | i tsi | ? ? 1.0 a v in = 0.5 to v cc ? 0.5 v res c in ? ? 10 pf v in = 0 v nmi ? ? 10 pf f = 1 mhz input capacitance all input pins except res and nmi ? ? 10 pf t a = 25c normal operation i cc * 3 ? 50 65 ma f = 33 mhz sleep mode ? 38 48 ma f = 33 mhz standby mode * 2 ? 30 90 a t a 50c current consumption * 1 ? ? 120 a 50c < t a ram standby voltage v ram 3.0 ? ? v vcc start power supply v ccstart ? 0 0.8 v * 4 vcc rising gradient sv cc ? ? 20 ms/v * 4 notes: 1. current consumption values are for v ih min = v cc ? 0.2 v and v il max = 0.2 v with all output pins unloaded. 2. the values are for v cc = 3.0 v, v ih min = v cc 0.9, and v il max = 0.3 v. 3. i cc depends on v cc and f as follows: i cc max = 6.5 (ma) + 0.49 (ma/(mhz v)) v cc f (normal operation) i cc max = 6.5 (ma) + 0.35 (ma/(mhz v)) v cc f (sleep mode) 4. these values are measured when the res pin is low.
rev. 2.00, 03/04, page 500 of 534 table 18.4 permissible output currents conditions: v cc = 3.0 v to 3.6 v, v ss = 0 v item symbol min. typ. max. unit ports 1 and 4 ? ? 1.6 permissible output low current (per pin) all output pins execept ports 1 and 4 i ol ? ? 2 ma permissible output low current (total) total of all output pins i ol ? ? 60 ma permissible output high current (per pin) all output pins ? i oh ? ? 2 ma permissible output high current (total) total of all output pins ? i oh ? ? 30 ma caution: 1. to protect the lsi?s reliability, do not exceed the output current values in table 18.4. 2. to drive the darlington transistor direct ly, inset a current-limit resister between the lsi and the transistor, as shown in figure 18.1. this lsi 2 k ? port darlington transistor figure 18.1 sample of dalington transistor drive circuit
rev. 2.00, 03/04, page 501 of 534 18.3 ac characteristics lsi output pin crh rl 3 v c = 50 pf: ports 5 to 9, port a c = 30 pf: ports 1 to 4 rl = 2.4 k ? rh = 12 k ? input/output timing measurement level: 1.5 v (v cc = 3.0 v to 3.6 v) figure 18.2 output load circuit 18.3.1 clock timing table 18.5 clock timing conditions: v cc = 3.0 v to 3.6 v, v ss = 0 v, = 10 mhz to 33 mhz item symbol min. max. unit test conditions clock cycle time t cyc 30.3 100 ns figure 18.3 clock pulse high width t ch 10 ? ns clock pulse low width t cl 10 ? ns clock rise time t cr ? 5 ns clock fall time t cf ? 5 ns reset oscillation stabilization time (crystal) t osc1 10 ? ms figure 18.4 8 ? ms < 30 mhz figure 18.5 software standby oscillation stabilization time (crystal) t osc2 3.9 ? ms 30 mhz external clock output delay stabilization time t dext 500 ? s figure 18.4
rev. 2.00, 03/04, page 502 of 534 t cyc t ch t cf t cl t cr input/output timing measurement level : low level : 0.8 v high level : 1.5 v figure 18.3 system clock timing extal v cc t dext t osc1 t dext t osc1 figure 18.4 oscillation stabilization timing (1) oscillator software standby mode (power-down mode) oscillation stabilization time t osc2 nmi nmi exception handling nmieg = 1 ssby = 1 nmi exception handling sleep instruction nmieg ssby figure 18.5 oscillation stabilization timing (2)
rev. 2.00, 03/04, page 503 of 534 18.3.2 control signal timing table 18.6 control signal timing conditions: v cc = 3.0 v to 3.6 v, v ss = 0 v, = 10 mhz to 33 mhz item symbol min. max. unit test conditions res setup time t ress 200 ? ns figure 18.6 res pulse width t resw 20 ? t cyc nmi setup time t nmis 150 ? ns figure 18.7 nmi hold time t nmih 10 ? nmi pulse width (in recovery from software standby mode) t nmiw 200 ? irq setup time t irqs 150 ? ns irq hold time t irqh 10 ? irq pulse width (in recovery from software standby mode) t irqw 200 ? t ress t ress t resw figure 18.6 reset input timing nmi (i = 0 to 7) (edge input) t nmis t nmih t irqs t irqs t irqh t nmiw t irqw (level input) figure 18.7 int errupt input timing
rev. 2.00, 03/04, page 504 of 534 18.3.3 bus timing table 18.7 bus timing (1) conditions: v cc = 3.0 v to 3.6 v, v ss = 0 v, = 10 mhz to 33 mhz item symbol min. max. unit test conditions address delay time t ad ? 20 ns address setup time 1 t as1 0.5 t cyc ? 13 ? ns figures 18.8 to 18.17 address setup time 2 t as2 1.0 t cyc ? 13 ? ns address setup time 3 t as3 1.5 t cyc ? 13 ? ns address setup time 4 t as4 2.0 t cyc ? 13 ? ns address hold time 1 t ah1 0.5 t cyc ? 8 ? ns address hold time 2 t ah2 1.0 t cyc ? 8 ? ns address hold time 3 t ah3 1.5 t cyc ? 8 ? ns cs delay time 1 t csd1 ? 15 ns cs delay time 2 t csd2 ? 15 ns cs delay time 3 t csd3 ? 20 ns as delay time t asd ? 15 ns rd delay time 1 t rsd1 ? 15 ns rd delay time 2 t rsd2 ? 15 ns read data setup time 1 t rds1 15 ? ns read data setup time 2 t rds2 15 ? ns read data hold time 1 t rdh1 0 ? ns read data hold time 2 t rdh2 0 ? ns read data access time 1 t ac1 ? 1.0 t cyc ? 25 ns read data access time 2 t ac2 ? 1.5 t cyc ? 25 ns read data access time 3 t ac3 ? 2.0 t cyc ? 25 ns read data access time 4 t ac4 ? 2.5 t cyc ? 25 ns read data access time 5 t ac5 ? 1.0 t cyc ? 25 ns read data access time 6 t ac6 ? 2.0 t cyc ? 25 ns read data access time 7 t ac7 ? 4.0 t cyc ? 25 ns read data access time 8 t ac8 ? 3.0 t cyc ? 25 ns address read data access time 2 t aa2 ? 1.5 t cyc ? 25 ns address read data access time 3 t aa3 ? 2.0 t cyc ? 25 ns address read data access time 4 t aa4 ? 2.5 t cyc ? 25 ns address read data access time 5 t aa5 ? 3.0 t cyc ? 25 ns
rev. 2.00, 03/04, page 505 of 534 table 18.8 bus timing (2) conditions: v cc = 3.0 v to 3.6 v, v ss = 0 v, = 10 mhz to 33 mhz item symbol min. max. unit test conditions wr delay time 1 t wrd1 ? 15 ns wr delay time 2 t wrd2 ? 15 ns figures 18.8 to 18.19 wr pulse width 1 t wsw1 1.0 t cyc ? 13 ? ns wr pulse width 2 t wsw2 1.5 t cyc ? 13 ? ns write data delay time t wdd ? 20 ns write data setup time 1 t wds1 0.5 t cyc ? 13 ? ns write data setup time 2 t wds2 1.0 t cyc ? 13 ? ns write data setup time 3 t wds3 1.5 t cyc ? 13 ? ns write data hold time 1 t wdh1 0.5 t cyc ? 8 ? ns write data hold time 2 t wdh2 1.0 t cyc ? 8 ? ns write data hold time 3 t wdh3 1.5 t cyc ? 8 ? ns write command setup time 1 t wcs1 0.5 t cyc ? 10 ? ns write command setup time 2 t wcs2 1.0 t cyc ? 10 ? ns write command hold time 1 t wch1 0.5 t cyc ? 10 ? ns write command hold time 2 t wch2 1.0 t cyc ? 10 ? ns read command setup time 1 t rcs1 1.5 t cyc ? 10 ? ns read command setup time 2 t rcs2 2.0 t cyc ? 10 ? ns read command hold time t rch 0.5 t cyc ? 10 ? ns cas delay time 1 t casd1 ? 15 ns cas delay time 2 t casd2 ? 15 ns cas setup time 1 t csr1 0.5 t cyc ? 10 ? ns cas setup time 2 t csr2 1.5 t cyc ? 10 ? ns cas pulse width 1 t casw1 1.0 t cyc ? 20 ? ns cas pulse width 2 t casw2 1.5 t cyc ? 20 ? ns cas precharge time 1 t cpw1 1.0 t cyc ? 20 ? ns cas precharge time 2 t cpw2 1.5 t cyc ? 20 ? ns oe delay time 1 t oed1 ? 15 ns oe delay time 2 t oed2 ? 15 ns precharge time 1 t pch1 1.0 t cyc ? 20 ? ns precharge time 2 t pch2 1.5 t cyc ? 20 ? ns self-refresh precharge time 1 t rps1 1.5 t cyc ? 20 ? ns self-refresh precharge time 2 t rps2 2.0 t cyc ? 20 ? ns
rev. 2.00, 03/04, page 506 of 534 t1 t2 a23 to a0 to d15 to d0 d15 to d0 , d15 to d0 read (rdnn = 1) read (rdnn = 0) write t ad t csd1 t as1 t as1 t as1 t as1 t rsd1 t rsd1 t ac5 t aa2 t rsd1 t wrd2 t wsw1 t wdh1 t wdd t wrd2 t ah1 t ac2 t rds2 t aa3 t rsd2 t rds1 t rdh1 t ah1 t asd t asd to t dacd1 t dacd2 t rdh2 figure 18.8 basic bus timing: two-state access
rev. 2.00, 03/04, page 507 of 534 t1 a23 to a0 to d15 to d0 d15 to d0 , d15 to d0 t2 t3 read (rdnn = 1) read (rdnn = 0) write t ad t as1 t ah1 t rsd1 t rds1 t rdh1 t rsd2 t rds2 t rdh2 t asd t asd t rsd1 t rsd1 t ac6 t ac4 t aa5 t as2 t wsw2 t wds1 t wrd1 t wrd2 t ah1 t aa4 t as1 t as1 t csd1 to t dacd1 t dacd2 t wdh1 t wdd figure 18.9 basic bus timing: three-state access
rev. 2.00, 03/04, page 508 of 534 th t ad t csd1 t as1 t asd t as3 t rsd1 t ac5 t rds1 t rdh1 t ah2 t ah3 t wdh3 t wsw1 t wds2 t wdd t as3 t wrd2 t wrd2 t rsd2 t rsd1 t ac2 t rds2 t rdh2 t as3 t rsd1 t ah3 t ah1 t asd a23 to a0 to d15 to d0 d15 to d0 , d15 to d0 t1 t2 tt read (rdnn = 1) read (rdnn = 0) write to t dacd1 t dacd2 figure 18.10 basic bus timing: two-state access ( cs assertion period extended)
rev. 2.00, 03/04, page 509 of 534 th t ad t csd1 t as1 t asd t as3 t rsd1 t rsd1 t asd t ah1 t ah3 t ah2 t ah3 t wdh3 t wsw2 t wds3 t as4 t as3 t rsd1 t wrd2 t wrd1 t ac4 t rdh2 t rsd2 t ac6 t rdh1 t1 t2 t3 tt a23 to a0 to d15 to d0 d15 to d0 d15 to d0 , read (rdnn = 1) read (rdnn = 0) write to t dacd1 t dacd2 t rds2 t wdd t rds1 figure 18.11 basic bus timing: three-state access ( cs assertion period extended)
rev. 2.00, 03/04, page 510 of 534 tp t ad t as3 t ah1 t csd2 t pch2 t as2 t ac1 t oed1 t oed1 t aa3 t ac4 t wcs1 t wch1 t wrd2 t wdd t wds1 t wdh2 t rds2 t rdh2 t ah2 t csd3 t casd1 t casd1 t casw1 t ad a23 to a0 , d15 to d0 , d15 to d0 tr tc1 tc2 read write to t dacd1 t dacd2 note: timing: when dds = 0 timing: when rast = 0 t wrd2 figure 18.12 dram acces s timing: two-state access
rev. 2.00, 03/04, page 511 of 534 tp a23 to a0 , d15 to d0 , d15 to d0 tr tc1 t cpw1 t ac3 t rch t rcs1 tc2 tc1 tc2 read write timing: when dds = 0 timing: when rast = 0 note: to t dacd1 t dacd2 figure 18.13 dram access timing: two-state burst access
rev. 2.00, 03/04, page 512 of 534 tp t ad t ad t as2 t ah2 t csd2 t pch1 t as3 t csd3 t casd1 t ah3 t casd2 t casw2 t ac2 t aa5 t ac7 t wrd2 t wdd t wds2 t wdh3 t wcs2 t wch2 t rdh2 t oed2 t oed1 a23 to a0 , d15 to d0 , d15 to d0 tr tc1 tc2 tc3 write read timing: when dds = 0 timing: when rast = 0 note: to t dacd1 t dacd2 t wrd2 t rds2 figure 18.14 dram access timing: thr ee-state access (rast = 1)
rev. 2.00, 03/04, page 513 of 534 tp tr tc1 tc2 tc3 tc1 tc2 tc3 a23 to a0 , d15 to d0 , t rch t rcs2 t ac8 t cpw2 d15 to d0 read write timing: when dds = 1 timing: when rast = 1 note: to figure 18.15 dram access timing: thr ee-state burst access
rev. 2.00, 03/04, page 514 of 534 trp , trr t csd2 t csr1 t casd1 t casd1 t csd1 trc1 trc2 figure 18.16 cas-before -ras refresh timing trp , trrw t csd2 t csr2 t casd1 t csd1 t casd1 trr trc1 trcw trc2 figure 18.17 cas-before -ras refresh timing (wit h wait cycle insertion) trp , trr t csd2 t casd1 t csd2 t casd1 t rps2 trc trc tpsr tp tr dram access self-refresh figure 18.18 self-refres h timing (return from software standby mode: rast = 0)
rev. 2.00, 03/04, page 515 of 534 trp , trr t csd2 t casd1 t csd2 t casd1 t rps1 trc trc tpsr tp tr dram access self-refresh figure 18.19 self-refres h timing (return from software standby mode: rast = 1) 18.3.4 dmac timing table 18.9 dmac timing conditions: v cc = 3.0 v to 3.6 v, v ss = 0 v, = 10 mhz to 33 mhz item symbol min. max. unit test conditions dreq setup time t drqs 25 ? ns figure 18.23 dreq hold time t drqh 10 ? tend delay time t ted ? 18 ns figure 18.22 dack delay time 1 t dacd1 ? 18 figures 18.20 and 18.21 dack delay time 2 t dacd2 ? 18
rev. 2.00, 03/04, page 516 of 534 t1 a23 to a0 to t dacd1 t dacd2 (read) d15 to d0 (read) , (write) d15 to d0 (write) to t2 figure 18.20 dmac single addre ss transfer timing: two-state access
rev. 2.00, 03/04, page 517 of 534 t1 t dacd1 t dacd2 a23 to a0 to (read) d15 to d0 (read) , (write) d15 to d0 (write) to t2 t3 figure 18.21 dmac single addre ss transfer timing: three-state access t1 t ted t ted t2 or t3 figure 18.22 dmac, tend output timing
rev. 2.00, 03/04, page 518 of 534 t drqs t drqh figure 18.23 dmac, dreq input timing 18.3.5 timing of on-chip peripheral modules table 18.10 timing of on -chip peripheral modules conditions: v cc = 3.0 v to 3.6 v, v ss = 0 v, = 10 mhz to 33 mhz item symbol min. max. unit test conditions i/o ports output data delay time t pwd ? 40 ns figure 18.24 input data setup time t prs 25 ? ns input data hold time t prh 25 ? ns 8-bit timer timer output delay time t tmod ? 40 ns figure 18.25 timer reset input setup time t tmrs 25 ? ns figure 18.27 timer clock input setup time t tmcs 25 ? ns figure 18.26 single-edge specification t tmcwh 1.5 ? t cyc timer clock pulse width both-edge specification t tmcwl 2.5 ? t cyc usb2 data output delay time t udo ? 18 ns figure 18.28 uswdvld output delay time t uwo ? 18 control output delay time t uco ? 18 data input setup time t uds 12 ? data input hold time t udh 2 ? uswdvld input setup time t uws 12 ? uswdvld input hold time t udh 2 ? control input setup time t uucs 12 ? control input hold time t udch 2 ?
rev. 2.00, 03/04, page 519 of 534 t1 t prs t prh t pwd t2 ports 1 to 9, ports a (read) ports 1 to 9, ports a (write) figure 18.24 i/o port input/output timing tmo0, tmo1 t tmod figure 18.25 8-bit timer output timing tmci0, tmci1 t tmcwl t tmcwh t tmcs t tmcs figure 18.26 8-bit timer clock input timing tmri0, tmri1 t tmrs figure 18.27 8-bit timer reset input timing
rev. 2.00, 03/04, page 520 of 534 data output (usd15 to usd0) uswdvld output control output (usxcvrs, usser, ustxv, , usopm1, usopm0) usclk t udo t uwo t uco data input (usd15 to usd0) uswdvld input control input (usrxact, usrxv, usrxerr, ustxrdy, uslsta1, uslsta0) usclk t uds t uws t ucs t udh t uwh t uch figure 18.28 usb2 input/output timing
rev. 2.00, 03/04, page 521 of 534 18.4 flash memory characteristics 18.4.1 flash memory characteristics table 18.11 flash memory characteristics conditions: v cc = 3.0 v to 3.6 v, v ss = 0 v item symbol min. typ. max. unit test conditions programming time * 1, * 2, * 4 t p ? 3 30 ms/128 bytes ? 80 800 ms/4 kbytes ? 500 5000 ms/32 kbytes erase time * 1, * 2, * 4 t e ? 1000 10000 ms/64 kbytes rewrite times (total) * 1, * 2, * 4 tp ? 5 15 s/256 kbytes ta = 25 c erase time (total) * 1, * 2, * 4 te ? 5 15 s/256 kbytes ta = 25 c programming and erase time (total) * 1, * 2, * 4 tpe ? 10 30 s/256 kbytes ta = 25 c count of rewriting n wec 100 * 3 ? ? times data hold time * 4 t drp 10 ? ? year notes: 1. the programming and er ase time depends on the data. 2. the programming and erase time does not include the data transfer time. 3. the minimum times that all characteri stics after rewriting are guaranteed. (a range between 1 and minimum value is guaranteed.) 4. data hold characteristics when rewriting is performed within the r ange of specifications including minimum value.
rev. 2.00, 03/04, page 522 of 534 18.5 use note (internal voltage step down) the h8s/2170 f-ztat have a voltage step down circuit that automatically lowers the power supply voltage, inside the microcomputer, to an adequate level. a capacitor (one 0.1- f capacitor) should be connected between the vcl pin (a pin for internal voltage step down circuit) and vss pin to stabilize the internal voltage. figure 18. 29 shows how to connect the capacitor. do not connect the v cc power-supply to the vcl pin. doing so could permanently damage the lsi. (connect the v cc power-supply to the v cc pin, in the usual way.) an external capacitor to stabilize the internal voltage one 0.1- f capacitor vcl vdo not connect the vcc power-supply to the vcl pin. if connected, the lsi may be permanently damaged. connect the vcc power-supply to the other vcc pin in the usual way. use a multilayer ceramic capacitor (one 0.1- f capacitor) for this circuit, and place it/them near the vcl pin. vss figure 18.29 vcl capa citor connection method
rev. 2.00, 03/04, page 523 of 534 appendix a. port states in each processing state port name pin name mcu operating mode reset hardware standby mode software standby mode program execution state sleep mode port 1 2 t t keep i/o port port 2 2 t t keep i/o port port 3 2 t t keep i/o port port 4 2 t t keep i/o port port 5 2 t t keep i/o port port 6 2 l t keep [address output] a15 to a8 port 7 2 l t keep [address output] a7 to a0 port 8 2 t t keep i/o port p97/ 2 clock output t [clock output] h [other than above] keep [clock output] clock output [other than above] input port p96/ as 2 h t keep [ as output] as [other than above] i/o port p95/ rd 2 h t h rd , hwr p94/ hwr 2 h t h rd , hwr p93/ lwr 2 h t [ lwr output] h [other than above] keep [ lwr output] lwr [other than above] i/o port
rev. 2.00, 03/04, page 524 of 534 port name pin name mcu operating mode reset hardware standby mode software standby mode program execution state sleep mode p92/ cs2 2 h t [ cs output] h [other than above] keep [ cs output] cs [other than above] i/o port p91/ cs1 2 h t [ cs output] h [other than above] keep [ cs output] cs [other than above] i/o port p90/ cs0 2 h t [ cs output] h [other than above] keep [ cs output] cs [other than above] i/o port pa3/a19/ cs3 2 t t keep [address output] a19 [ cs output] cs [other than above] i/o port pa2/a18/ ucas 2 t t keep [ ucas and address output] ucas , a18 [other than above] i/o port pa1/a17/ lcas 2 t t keep [ lcas and address output] lcas , a17 [other than above] i/o port
rev. 2.00, 03/04, page 525 of 534 port name pin name mcu operating mode reset hardware standby mode software standby mode program execution state sleep mode pa0/a16 2 t t keep [address output] a16 [other than above] i/o port [legend] l: low level h: high level keep: input port becomes high-imp edance, output port retains state t: high impedance ddr: data direction register ope: output port enable b. product lineup product classification type name model marking package (code) h8s/2170 f-ztat version HD64F2170 HD64F2170 100-pin tqfp (tfp-100b)
rev. 2.00, 03/04, page 526 of 534 c. package dimensions package code jedec jeita mass (reference value) tfp-100b ? conforms 0.5 g * dimension including the plating thickness base material dimension 16.0 0.2 14 0.08 0.10 0.5 0.1 16.0 0.2 0.5 0.10 0.10 1.20 max * 0.17 0.05 0? ? 8? 75 51 125 76 100 26 50 m * 0.22 0.05 1.0 1.00 1.0 0.20 0.04 0.15 0.04 figure c.1 package dimensions (tfp-100b)
rev. 2.00, 03/04, page 527 of 534 main revisions and add itions in this edition item page revisions (s ee manual for details) section 4 exception handling 4.3.1 reset exception handling figure 4.1 reset sequence 58 description added (1), (3) reset exception handling vector address ((1) = h'000000, (3) = h'000002) section 10 watchdog timer (wdt) 10.2.2 timer control/ status register (tcsr) 285 bits2 to 0 amended 101: /8192 (frequency: 63.5 ms) section 12 universal serial bus 2 (usb2) 12.1 features 319 description added ? supports the usb version 2.0 ? supports four endpoints; ep0, ep1, ep2, and ep3 12.3.16 fifo clear register 0 (fclr0) 334 description added ep2 having a dual-fifo confi guration is cleared by entire fifos. similarly, as fo r ep1 fifo with a dual-fifo configuration, the only side cu rrently selected is cleared. 12.3.18 dma set register 0 (dma0) 336 description added that is, when there is no vali d data in the fifo even with one side, the transfer is requested to the dmac. 12.5.1 usb cable connection figure 12.2 usb cable connection 341 description added d+ pull-up on receive bus reset brst in ifr0 = 1
rev. 2.00, 03/04, page 528 of 534 item page revisions (s ee manual for details) 12.5.3 control transfer figure 12.6 data stage operation (control-in) 345 description added write number of transmit data bytes to packet enable register 0i (pkte0i) every packet. write data to ep0i data register (epdr0i) 12.5.3 control transfer figure 12.9 status stage operation (control-out) 348 description added clear interrupt flag (ep0i tr in ifr0 = 0) write 0 to packet enable register 0i (pkte0i) ep0i transfer request interrupt prohibited (ep0i tr in ier0 = 0) 12.5.5 ep2 bulk-in transfer (dual fifo) figure 12.11 ep2 bulk-in transfer operation 352 description amended 12.8.11 epdr0s read 366 description deleted epdr0s must be read in 8-byte units. if read is suspended, data received in the next setup cannot be read normally.
rev. 2.00, 03/04, page 529 of 534 item page revisions (s ee manual for details) 12.8.14 example of external circuit figure 12.18 connection example of external circuit 367 figure 12.18 amended usxcvrs ustsel usclk usrxact usrxv usrxerr ustxv ustxrdy usd15 to usd0 uswdvld ussusp uslsta1, uslsta0 usopm1 usopm0 dp dm xcvrselect termselect clk rxactive rxvalid (rxvalidh) rxerror txvalid (txvalidh) txready data15 to data0 validh suspendm linestate [1:0] opmode [1] opmode [0] rst (assert h) vbus (5 v) (3.3 v) usvbus res reset signal power-supply voltage can be applied to this ic even when the system (lsi) power is off. level shifter this lsi external physical layer lsi in the utmi specification usb connector figure 12.20 bus reset detection flow 369 description added 12.8.18 usb interrupt during software standby description added section 14 flash memory (0.18- m f-ztat version) 14.10 usage notes 462 description added 16. while writing 1 to the sco bit and downloading the internal programs, the wdt c outup operation stops. section 15 clock pulse generator 15.3.3 note on confirming the operation 467 description added description amended item symbol value unit operating temperature t opr regular specifications: ? 20 to + 75 c wide-range specifications: ? 40 to + 85 c operating temperature (flashmemory programing/erasure) t opr 0 to + 75 c section 18 electrical characteristics 18.1 absolute maximum ratings table 18.1 absolute maximum ratings 497 18.5 use note (internal voltage step down) 522 description amended a capacitor (one 0.1- f capacitor) should be connected between the vcl pin (a pin for internal voltage step down circuit) and vss pin to stabilize the internal voltage.
rev. 2.00, 03/04, page 530 of 534 item page revisions (s ee manual for details) figure 18.29 vcl capacitor connection method 522 figure 18.29 amended an external capacitor to stabilize the internal voltage one 0.1- f capacitor vcl vdo not connect the vcc power-supply to the vcl pin. if connected, the lsi may be permanently damaged. connect the vcc power-supply to the other vcc pin in the usual way. use a multilayer ceramic capacitor (one 0.1- f capacitor) for this circuit, and place it/them near the vcl pin. vss
rev. 2.00, 03/04, page 531 of 534 index 8-bit timer (tmr) ................................. 263 16-bit counter mode.......................... 274 cascaded conn ection.......................... 274 compare match count mode ............. 275 pulse output ....................................... 270 tcnt incrementation timing ............ 271 toggle output...................................... 279 address map............................................. 53 address space..................................... 16, 20 addressing mode...................................... 40 absolute address.................................. 41 immediate ............................................. 42 memory indirect ................................... 42 program-counter relative .................... 42 register direct...................................... 41 register indirect ................................... 41 register indirect with displacement..... 41 register indirect with post-increment...................................... 41 register indirect with pre-decrement.... 41 bcc...................................................... 29, 37 boot mode .............................................. 401 bulk-in transfer ..................................... 351 bulk-out transfer................................... 349 bus arbitration ....................................... 151 bus controller (bsc) ............................... 83 basic timing....................................... 110 chip select signals ............................. 108 data size and data alignment............ 109 extension of chip select ( cs ) assertion period.................................. 121 read strobe (rd) timing................... 120 valid strobes ...................................... 110 wait control ....................................... 119 clock pulse generator ............................ 463 communications protocol....................... 437 condition fi eld ......................................... 39 condition-code re gister (ccr) ............... 24 control transfer...................................... 343 cpu operating modes.............................. 16 advanced mode .................................... 18 normal mode ........................................ 16 crystal resonator.................................... 463 data direction register............................. 219 data register............................................ 219 dma controller (dmac) ...................... 153 channel prio rity .................................. 186 dual address mode ............................ 189 interrupt sources................................. 213 repeat area function ......................... 179 single address mode .......................... 196 transfer modes ................................... 171 dma transfer specifications ................. 358 dram interface ..................................... 122 effective address................................ 40, 44 effective address extension ....................... 39 effective address extension..................... 39 error protection....................................... 429 exception handling .................................. 55 exception handling vector table............. 56 extended control register (exr) ............ 23 flash mat configuration....................... 377 general registers ...................................... 22 hardware protection ............................... 428
rev. 2.00, 03/04, page 532 of 534 hardware stan dby mode ........................ 476 idle cycle ............................................... 142 instruction set........................................... 29 arithmetic operations instructions....... 32 bit manipulation instructions ............... 35 block data transfer instruction ........... 39 branch instructions............................... 37 data transfer instructions .................... 31 logic operations instructions............... 34 shift instructions .................................. 34 system control instruction ................... 38 interrupt control modes ........................... 72 interrupt controller................................... 63 interrupt exception handling ................... 59 interrupt exception handling sequence................................................... 78 interrupt exception handling vector table ............................................. 70 interrupt mask bit .................................... 24 interrupt request mask level .................. 23 interrupt-in transfer ............................... 353 interrupts cmia.................................................. 275 cmib.................................................. 275 eri0.................................................... 314 irq7 to irq0 interrupts....................... 69 nmi interrupt ....................................... 69 ovi..................................................... 275 rxi0 ................................................... 314 tei0.................................................... 314 txi0 ................................................... 314 wovi ................................................. 288 interval timer mode............................... 287 list of registers...................................... 479 register addresses ............................. 480 register bits ....................................... 485 register states in each operating mode................................................... 493 mode comparison................................... 376 module stop mode ................................. 477 on-board programming.......................... 401 on-board programming mode ................. 373 operating modes....................................... 49 operation field ......................................... 39 overflow.................................................. 286 pll circuit ............................................. 466 port register............................................. 219 power-down modes ............................... 469 procedure program ................................. 418 processing of usb standard requests and class/vendor requests..................... 354 program counter (pc) .............................. 23 programmer mode .................................. 434 programming/erasing interface parameter download pass/fail result parameter... 393 flash erase block select parameter...... 398 flash multipurpose address area parameter ............................................ 396 flash multipurpose data destination parameter ........................................... 396 flash pass/fail parameter..................... 399 flash programming/erasing frequency parameter ............................................ 394 programming/erasing interface register ................................................... 382 protection................................................ 428 ram ....................................................... 371 register field............................................ 39 registers abrkcr...................... 65, 482, 490, 495 acscr ......................... 87, 480, 487, 493 bcr .............................. 92, 481, 487, 493 brr ............................ 300, 483, 491, 495 csacr ......................... 88, 480, 487, 493
rev. 2.00, 03/04, page 533 of 534 ctrl.......................... 337, 480, 487, 493 dasts0 ..................... 332, 480, 486, 493 dma0......................... 336, 480, 487, 493 dmacr ..................... 165, 481, 488, 494 dmdar ..................... 158, 481, 488, 494 dmmdr..................... 160, 481, 488, 494 dmsar...................... 158, 481, 488, 494 dmtcr...................... 158, 481, 488, 494 draccr...................... 97, 481, 487, 494 dramcr..................... 94, 481, 487, 494 epdr0........................ 330, 480, 485, 493 epdr1........................ 331, 480, 486, 493 epdr2........................ 331, 480, 486, 493 epdr3........................ 332, 480, 486, 493 epstl0 ...................... 336, 480, 487, 493 epsz........................... 329, 480, 485, 493 fccs .......................... 382, 481, 488, 494 fclr0 ........................ 334, 480, 487, 493 fecs........................... 386, 481, 488, 494 fkey.......................... 387, 481, 488, 494 fmats....................... 388, 481, 488, 494 fpcs........................... 386, 481, 488, 494 ftdar ....................... 389, 481, 488, 494 icr ............................... 64, 482, 490, 495 ier................................ 68, 482, 490, 495 ier0............................ 329, 480, 485, 493 ifr0............................ 323, 480, 485, 493 iscr ............................. 67, 482, 490, 495 isr................................ 68, 482, 490, 495 isr0............................ 328, 480, 485, 493 issr............................ 262, 482, 490, 495 mdcr .......................... 50, 480, 487, 493 mstpcr .................... 473, 480, 487, 493 p1ddr ....................... 222, 482, 490, 495 p1dr .......................... 223, 483, 491, 496 p2ddr ....................... 226, 482, 490, 495 p2dr .......................... 226, 483, 491, 496 p3ddr ....................... 230, 482, 490, 495 p3dr .......................... 230, 483, 491, 496 p4ddr ....................... 233, 482, 490, 495 p4dr .......................... 234, 483, 491, 496 p5ddr ....................... 237, 482, 490, 495 p5dr .......................... 237, 483, 491, 496 p6ddr........................ 242, 482, 490, 495 p6dr........................... 242, 483, 491, 496 p7ddr........................ 246, 482, 491, 495 p7dr........................... 247, 483, 491, 496 p8ddr........................ 251, 483, 491, 495 p8dr........................... 251, 483, 491, 496 p9ddr........................ 254, 483, 491, 495 p9dr........................... 255, 483, 491, 496 paddr....................... 258, 483, 491, 495 padr.......................... 258, 483, 491, 496 pbar ............................ 66, 482, 490, 495 pfcr1......................... 261, 482, 490, 495 pfcr3......................... 338, 482, 490, 495 pkte .......................... 333, 480, 486, 493 port1 ........................ 223, 483, 491, 495 port2 ........................ 227, 483, 491, 495 port3 ........................ 231, 483, 491, 496 port4 ........................ 234, 483, 491, 496 port5 ........................ 238, 483, 491, 496 port6 ........................ 243, 483, 491, 496 port7 ........................ 247, 483, 491, 496 port8 ........................ 252, 483, 491, 496 port9 ........................ 255, 483, 491, 496 porta ....................... 259, 483, 491, 496 ramer ...................... 390, 481, 487, 493 rdncr......................... 93, 481, 487, 493 rdr ............................ 293, 483, 491, 495 refcr.......................... 98, 481, 488, 494 rsr..................................................... 293 rtcnt ....................... 101, 481, 488, 494 rtcor ....................... 101, 481, 488, 494 sbycr ....................... 472, 480, 487, 493 scr............................. 295, 483, 491, 495 smr ............................ 294, 483, 491, 495 ssr ............................. 297, 483, 491, 495 syscr.......................... 51, 480, 487, 493 tcnt ......................... 265, 284, 481, 484, .................................... 488, 492, 494, 496 tcora....................... 266, 484, 492, 496 tcorb ....................... 266, 484, 492, 496 tcr............................. 266, 483, 491, 496 tcsr ......................... 268, 284, 481, 483, .................................... 488, 491, 494, 496
rev. 2.00, 03/04, page 534 of 534 tdr .............................293, 483, 491, 495 tsr..................................................... 294 usbsusp....................338, 480, 487, 493 ustcr ........................169, 482, 490, 495 wtcr ...........................90, 481, 487, 493 reset ......................................................... 57 reset exception handling ........................ 57 serial communication interface (sci) ....................................................... 291 asynchronous mode........................... 304 bit rate ................................................ 300 framing error...................................... 310 overrun error ...................................... 310 parity error.......................................... 310 serial communication interface specificatio n ........................................... 435 sleep mode............................................. 474 software protection ................................ 429 software sta ndby mode ......................... 474 stack pointer (sp)..................................... 22 stack status .............................................. 60 stall operations....................................... 355 trace bit ................................................... 23 trap instruction exception handling........ 59 trapa instruc tion ............................. 42, 59 universal serial bus (usb2) .................. 319 usb cable conn ection ........................... 341 usb cable disconnection ...................... 342 user boot mat........................................ 431 user boot memory mat.......................... 373 user boot mode...................................... 415 user mat................................................ 431 user memory mat.................................. 373 user program mode................................ 405 watchdog timer (wdt)......................... 283 watchdog timer mode ........................... 286 write data buffer function .................... 150
renesas 16-bit single-chip microcomputer hardware manual h8s/2172 group publication date: 1st edition mar, 2003 rev.2.00 mar 17, 2004 published by: sales strategic planning div. renesas technology corp. edited by: technical documentation & information department renesas kodaira semiconductor co., ltd. ? 2004. renesas technology corp., all rights reserved. printed in japan.
colophon 1.0 sales strategic planning div. nippon bldg., 2-6-2, ohte-machi, chiyoda-ku, tokyo 100-0004, japan http://www.renesas.com renesas technology america, inc. 450 holger way, san jose, ca 95134-1368, u.s.a tel: <1> (408) 382-7500 fax: <1> (408) 382-7501 renesas technology europe limited. dukes meadow, millboard road, bourne end, buckinghamshire, sl8 5fh, united kingdom tel: <44> (1628) 585 100, fax: <44> (1628) 585 900 renesas technology europe gmbh dornacher str. 3, d-85622 feldkirchen, germany tel: <49> (89) 380 70 0, fax: <49> (89) 929 30 11 renesas technology hong kong ltd. 7/f., north tower, world finance centre, harbour city, canton road, hong kong tel: <852> 2265-6688, fax: <852> 2375-6836 renesas technology taiwan co., ltd. fl 10, #99, fu-hsing n. rd., taipei, taiwan tel: <886> (2) 2715-2888, fax: <886> (2) 2713-2999 renesas technology (shanghai) co., ltd. 26/f., ruijin building, no.205 maoming road (s), shanghai 200020, china tel: <86> (21) 6472-1001, fax: <86> (21) 6415-2952 renesas technology singapore pte. ltd. 1, harbour front avenue, #06-10, keppel bay tower, singapore 098632 tel: <65> 6213-0200, fax: <65> 6278-8001 renesas sales offices

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